https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789
--- Comment #5 from Craig Topper ---
Isn’t -mstrict-align the default? It is in LLVM.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114963
Bug ID: 114963
Summary: RISCV -msave-restore -fno-omit-frame-pointer does not
emit save/restore library calls
Product: gcc
Version: unknown
Status: UNCONFIRMED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095
--- Comment #3 from Craig Topper ---
Our FPGA data is showing this as a 5% regression. I'll try to check on an
Unmatched board to confirm.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095
--- Comment #2 from Craig Topper ---
The branch+mv macrofusion should execute together. The visible latency to other
instructions is 1 cycle.
The hardware can predicate most ALU instructions, not just mv. So even better
would be putting the xor
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095
Bug ID: 113095
Summary: RISC-V: movcc no longer used for coremark crc
functions with -mtune=sifive-7-series
Product: gcc
Version: 13.2.1
Status: UNCONFIRMED
Se
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201
--- Comment #7 from Craig Topper ---
Here is my attempt and defining scalar crypto intrinsics
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201
--- Comment #3 from Craig Topper ---
I don't have a testsuite. I saw that gcc had crypto builtins and I happened to
noticed the tests in gcc weren't passing constant arguments.
We also have a divergence in names between clang and gcc for some c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201
Bug ID: 110201
Summary: RISC-V: __builtin_riscv_sm4ks and
__builtin_riscv_sm4ed produce invalid assembly
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severit
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109972
Bug ID: 109972
Summary: RISC-V: Could use umodsi3/udivsi3/divsi3 libcalls for
32-bit division/remainder on RV64 without M extension
Product: gcc
Version: 14.0
Status: UN