https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789
--- Comment #5 from Craig Topper ---
Isn’t -mstrict-align the default? It is in LLVM.
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
It appears that combining -msave-restore and -fno-omit-frame-pointer results in
no save/restore library
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095
--- Comment #3 from Craig Topper ---
Our FPGA data is showing this as a 5% regression. I'll try to check on an
Unmatched board to confirm.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113095
--- Comment #2 from Craig Topper ---
The branch+mv macrofusion should execute together. The visible latency to other
instructions is 1 cycle.
The hardware can predicate most ALU instructions, not just mv. So even better
would be putting the xor
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
In gcc 12, the crc functions in coremark used the "movcc" macrofusion pattern
of a branch over a
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201
--- Comment #7 from Craig Topper ---
Here is my attempt and defining scalar crypto intrinsics
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110201
--- Comment #3 from Craig Topper ---
I don't have a testsuite. I saw that gcc had crypto builtins and I happened to
noticed the tests in gcc weren't passing constant arguments.
We also have a divergence in names between clang and gcc for some c
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
The __builtin_riscv_sm4ks and __builtin_riscv_sm4ed builtins don't enforce that
the byte select should
: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
There's an opportunity to improve code size for 32-bit division and remainder
on
onent: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
Cooperlake appears to be defined the enum in libgcc for __builtin_cpu_is, but
there is no code to use that enum value when identifying the cpu in libgcc.
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
Brand id or brand index was a feature that briefly existed in some Pentium III
and Pentium 4 CPUs. The code will only look at
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95121
Craig Topper changed:
What|Removed |Added
CC||craig.topper at gmail dot com
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
gcc supports some modifiers for inline assembly on X86 that are not documented
in the table at 6.47.2.8 x86 Operand
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
This intrinsic should always do a signed compare, but it uses __v32qi in its
implementation which uses "char" r
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91696
--- Comment #1 from Craig Topper ---
I've also submitted a patch to clang to do the same.
https://reviews.llvm.org/D67289
: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
The intrinsics that only support SAE like
: UNCONFIRMED
Severity: normal
Priority: P3
Component: libgcc
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
GFNI has instructions that have legacy SSE-like encodings. It also has VEX and
EVEX
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
These intrinsics are both blends of four 32-bit values. gcc seems to check the
range for the floating point
: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
It looks like gcc does not match the behavior of the most recent versions of
icc, clang, and
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
icc has these intrinsics which emulate a v8di multiply using multiple pmuludqs
when avx512f is enabled, but avx512dq is not
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85511
--- Comment #2 from Craig Topper ---
Should this builtin even be allowed in 64-bit mode?
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
This code
void foo(unsigned bar) {
return __builtin_ia32_writeeflags_u32(bar);
}
Throws this error
erity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
Trying to compile the _rdpid_u32 intrinsic on x86-64 causes the assembler to
print this
/tmp/ccbdTr5q.s: Asse
ormal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
The documentation https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html says
'silvermont' enables rdrnd, but that
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80042
--- Comment #3 from Craig Topper ---
No -fmath-errno has no effect. It does have effect on other functions such as
cosh or acos.
e-end
Assignee: unassigned at gcc dot gnu.org
Reporter: craig.topper at gmail dot com
Target Milestone: ---
Created attachment 40974
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40974&action=edit
Test that uses sin and errno
As of glibc version 2.10, sin and cos se
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50740
Bug #: 50740
Summary: CPUID leaf 7 for BMI/BMI2/AVX2 feature detection not
qualified with max_level and doesn't use subleaf
Classification: Unclassified
Product: gcc
Version: unk
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