https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120439
--- Comment #7 from camel-cdr ---
I suppose it's a question about the intrinsics contract.
The intrinsics by them self don't expose register assignment and don't give you
a way to control it.
Consider the following:
static vuint8m1_t bar(
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120439
Bug ID: 120439
Summary: RVV: wrong tail/mask-policy when source and
destination overlap with different EEW
Product: gcc
Version: 16.0
Status: UNCONFIRMED
Sever
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373
--- Comment #9 from camel-cdr ---
Sorry, I missed that you attached the relevant C code.
Here is a side by side with and without -m-rvv-lmul-max=dynamic:
https://godbolt.org/z/MToxx813v
Using LLVM-MCA as a quick and dirty performance model show
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119373
camel-cdr changed:
What|Removed |Added
CC||camel-cdr at protonmail dot com
--- Comment
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114686
Bug ID: 114686
Summary: Feature request: Dynamic LMUL should be the default
for the RISC-V Vector extension
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Seve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114194
Bug ID: 114194
Summary: ICE when using std::unique_ptr with xtheadvector
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114180
Bug ID: 114180
Summary: RISC-V: missing vsetvl changes tail policy and causes
wrong codegen
Product: gcc
Version: 13.2.0
Status: UNCONFIRMED
Severity: normal
