ipa vrp implementation in gcc

sense? Any thoughts/suggestions to work on this is highly appreciated. Thanks, Kugan

Re: ipa vrp implementation in gcc

place (or post it here) so that we know what you plans are. That way we can work on what you are not working. And also possible contribute to your plan in other ways (like testing and reviewing). Thanks, Kugan

Re: ipa vrp implementation in gcc

stored in aggregates > for that we need better separate representaiton > > See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68930 >> Thanks, Kugan

Re: ipa vrp implementation in gcc

prototype Richard Biener implemented available anywhere. Can you please point me to that. Thanks, Kugan IPA structures before propagation: Function parameters: function foo/6 parameter descriptors: param #0 used undescribed_use function main/3 parameter descriptors: function bar2/1

Re: ipa vrp implementation in gcc

ion 3 bar1 (a, b); } else { //region 4 bar2 (a, b); } } else { //region 5 bar3 (a, b); } bar4 (a, b); } I am also wondering whether we should split the live ranges to get better value ranges (for the example shown above)? Thanks, Kugan

fstrict-enums and value ranges in VRP

be valid if the program uses a cast to convert an arbitrary integer value to the enumerated type. Thanks, Kugan

Re: anti-ranges of signed variables

= ri->get_max (); - return SSA_NAME_RANGE_TYPE (name); + return SSA_NAME_RANGE_TYPE (name) ? VR_ANTI_RANGE : VR_RANGE; } Is this OK after testing ? Thanks, Kugan

Re: anti-ranges of signed variables

So, we shouldn't do it again. Sorry about the noise. Kugan

Using particular register class (like floating point registers) as spill register class

is not going to help. If I increase further, register allocated will just spill these live ranges to memory and will ignore floating point register in this case. Is there any other back-end in gcc that does anything to improve cases like this, that I can refer to? Thanks in advance, Kugan

Re: Using particular register class (like floating point registers) as spill register class

On 16/05/14 20:40, pins...@gmail.com wrote: > > >> On May 16, 2014, at 3:23 AM, Kugan wrote: >> >> I would like to know if there is anyway we can use registers from >> particular register class just as spill registers (in places where >> register allocat

Zero/Sign extension elimination using value ranges

sense? Thanks, Kugan

Re: Zero/Sign extension elimination using value ranges

On 20/05/14 16:52, Jakub Jelinek wrote: > On Tue, May 20, 2014 at 12:27:31PM +1000, Kugan wrote: >> 1. Handling NOP_EXPR or CONVERT_EXPR that are in the IL because they >> are required for type correctness. We have two cases here: >> >> A) Mode is smaller than word

Re: Zero/Sign extension elimination using value ranges

On 21/05/14 17:05, Jakub Jelinek wrote: > On Wed, May 21, 2014 at 12:53:47PM +1000, Kugan wrote: >> On 20/05/14 16:52, Jakub Jelinek wrote: >>> On Tue, May 20, 2014 at 12:27:31PM +1000, Kugan wrote: >>>> 1. Handling NOP_EXPR or CONVERT_EXPR that are in the IL beca

Re: Zero/Sign extension elimination using value ranges

G_PROMOTED_GET", (RTX), SUBREG))->volatil)\ + (RTX)->unchanging - 1) #define SUBREG_PROMOTED_SIGNED_P(RTX) \ RTL_FLAG_CHECK1 ("SUBREG_PROMOTED_SIGNED_P", (RTX), SUBREG)->volatil)\ + (RTX)->unchanging) == 0) ? 0 : ((RTX)->unchanging == 1)) #define SUB

Question about LRA in aarch64_be-none-elf

? Thanks, Kugan t.c.214r.reload --- (insn 88 87 133 3 (clobber (reg:TI 32 v0 [orig:108 d+-8 ] [108])) t.c:11 -1 (nil)) ---89, 134 and 91 stores (insn 133 88 89 3 (set (mem/c:TI (plus:DI (reg/f:DI 29 x29) (const_int 64 [0x40])) [0 %sfp+-16 S16 A128]) (reg:TI

reg_equiv_mem and reg_equiv_address are NULL for true_regnum == -1

Hi All, I am looking at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62254. Here, in arm_reload_in, for REG_P (ref) which has true_regnum (ref) == -1, both reg_equiv_mem (REG_P (ref)) and reg_equiv_address (REG_P (ref)) are NULL. Can this happen? Thanks, Kugan

Re: A Question About LRA/reload

ent. Please look at the following links for more info. https://ols.fedoraproject.org/GCC/Reprints-2007/makarov-reprint.pdf https://gcc.gnu.org/wiki/cauldron2012?action=AttachFile&do=get&target=Local_Register_Allocator_Project_Detail.pdf Thanks, Kugan

Re: A Question About LRA/reload

On 09/12/14 21:14, lin zuojian wrote: > Hi Kugan, > I have read these pdfs. My question is LRA will change the insns, so > why brother do the coloring so early. Changing the insns can > generates new pseudo registers, so they needs to re-assign. Is that > correct?

Re: issue with placing includes in gcc-plugin.h

[1]: *** [stage1-bubble] Error 2 > make: *** [all] Error 2 > > Why do the front-ends require to include plugin.h ? C/C++ Front-end seems to have callbacks to process declarations. Please look at https://gcc.gnu.org/ml/gcc-patches/2010-04/msg00780.html which added callback PLUGIN_FINISH_DECL. Thanks, Kugan

loop_latch_edge is NULL during jump threading

., loops with more than one entry block), and Thanks, Kugan

Re: loop_latch_edge is NULL during jump threading

On 02/03/15 15:29, Jeff Law wrote: > On 03/01/15 16:32, Kugan wrote: >> In linaro-4.9-branch, with the following (reduced) test case, I run into >> a situation where loop_latch_edge is NULL during jump threading. I am >> wondering if this a possible during jump threading or t

Re: Combine changes ASHIFT into mult for non-MEM rtx

), is it reasonable to fix this behavior in > combine.c? Another question is, if we are going to make the change, > how many targets might be affected? > I think https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01020.html is related to this. Thanks, kugan

Re: optimization question

c.gnu.org/wiki/A_guide_to_testcase_reduction There are some examples/techniques to create a reduced test-case that reproduces it. Thanks, Kugan

Re: LTO crashes with fortran code in SPEC CPU 2006

ortran returned 1 exit status I don't know when this started as I am just starting to run SPEC CPU 2006 fp side with my spec cpu 2006 config. I am seeing this too for aatch64 with -O3 -flto. It did work few weeks back. This must be a new bug. Thanks, Kugan Thanks, Andrew

[PR43721] Failure to optimise (a/b) and (a%b) into single call

specific and can be obtained from sdivmod_optab so the builtin function name defined in tree level is not used. I am not entirelt sure this is the right approach so I am attaching the first cut of the patch to get your feedback and understand the right approach to this problem. Thank you, Kugan

Re: [PR43721] Failure to optimise (a/b) and (a%b) into single call

On 17/06/13 19:07, Richard Biener wrote: On Mon, 17 Jun 2013, Kugan wrote: Hi, I am attempting to fix Bug 43721 - Failure to optimise (a/b) and (a%b) into single __aeabi_idivmod call (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43721) execute_cse_sincos tree level pass does similar cse so I

Re: On-Demand range technology [1/5] - Executive Summary

it is not possible to get value ranges in PROMOTED_MODE precision on demand. Or is there any way we can use on-demand ranger here? Thanks, Kugan On Thu, 23 May 2019 at 11:28, Andrew MacLeod wrote: > > Now that stage 1 has reopened, I’d like to reopen a discussion about the > techn

Re: On-Demand range technology [1/5] - Executive Summary

precision, the patch would be correct and used to eliminate redundant zero/sign extensions. Please let me know if my explanation is not clear and I will show it with more examples. Thanks, Kugan On Fri, 21 Jun 2019 at 23:27, Andrew MacLeod wrote: > > On 6/19/19 11:04 PM, Kugan Vivekanandarajah

Re: Duplicating loops and virtual phis

are also looking at this problem and looking forward to seeing the patches. I have some experimental patches where I added the data reference that needs runtime checking to a list static int pg_add_dependence_edges (struct graph *rdg, vec loops, int dir, vec drs1, - vec drs2) + vec drs2, + vec &ddrs, + bool runtime_alias_check) Then I am vesioning the main loop based on the condition generated from the runtime check. I have borrowed the logic from vectorizer (like pruning the list and generating the condition). I have neither verified nor benchmarked it enough yet. As I understand, we also should have some form of cost model where we should be able too see the data access patterns and decide if the distributed loops can be vectorized? Cost model in similar_memory_accesses also need to be relaxd based on the ability to vectorize distributed loops. Thanks, Kugan > Thanks, > bin >> >> Richard. >> >>>Steve Ellcey >>>sell...@cavium.com >>

Loop reversal

taught to select the reverse iv ? 2. Or is the patch by Zdenek a better option. I am re-basing it for the trunk. Thanks, Kugan

Re: [RFC] type promotion pass

> those promotions also apply to function calls and arguments and those are > difficult to break apart from other ABI specific details. > > IIRC the last time we went over this patch I concluded a better first step > would be to expose call ABI details on GIMPLE much earlier. But I may > misremember here. I think this would be very useful. Some of the regressions in type promotion comes from parameters/return values. ABI in some cases guarantees that they are properly extended but during type promotion we promote (or extend) leading to additional extensions. We might also need some way of having gimple statements that can convert (or promote to the type without extensions) just to keep the gimple type system happy. Thanks, Kugan > > Basically we couldn't really apply all promotions RTL expansion applies. One > of my ideas with doing them early also was to simplify RTL expansion and > especially promotion issues during SSA coalescing. > > Richard. > >>jeff >

Re: [RFC] type promotion pass

here. I haven't looked in detail yet but -fno-tree-forwprop seems to remove 6 "and" from the test case. I have a slightly different version to what Prathamseh has posted and hope that there isn't any difference here. Thanks, Kugan

Handling prefetcher tag collisions while allocating registers

scratch registers to manage this. We can do a machine reorg pass in gcc but detecting strided loads at that stage is not easy. I am trying to implement this in gcc and wondering what is the preferred and acceptable way to implement this. Any thoughts ? Thanks, Kugan

Re: Handling prefetcher tag collisions while allocating registers

Hi Bin, On 24 October 2017 at 18:29, Bin.Cheng wrote: > On Tue, Oct 24, 2017 at 12:44 AM, Kugan Vivekanandarajah > wrote: >> Hi All, >> >> I am wondering if there is anyway we can prefer certain registers in >> register allocations. That is, I want to have som

Re: Global analysis of RTL

ine representation. An obvious example is, in RTL sign is not represented. Even in RTL, after reload, we will have one to one mapping fro RTL to actual machine instruction (i.e. more closer to asm). In short, gcc goes from generic to gimple to RTL as stamens are lowered from high level languages to as

Re: Problems in IPA passes

may not be > initialized when IPA runs (vrp_equiv_obstack, vr_value). IPA-VRP does not track equivalence and vr_value is not used. Thanks, Kugan > > While this seems to be working today, it's a failure waiting to happen. > > Is there any way you can avoid using those rou

Re: Problems in IPA passes

Hi Jeff, On 31 October 2017 at 14:47, Jeff Law wrote: > On 10/29/2017 03:54 PM, Kugan Vivekanandarajah wrote: >> Hi Jeff, >> >> On 28 October 2017 at 18:28, Jeff Law wrote: >>> >>> Jan, >>> >>> What's the purpose behind calling vrp_

Re: poly_uint64 / TYPE_VECTOR_SUBPARTS question

FIK, you could use to_constant () if known to be a compile time constant. Thanks, Kugan > > My first thought was that I was missing a header file but I put > all the header includes that are in i386.c into aarch64-builtins.c > and it still does not compile. It works on the i386 s

Generating gimple assign stmt that changes sign

examples I can refer to. Conversion expressions seems to be the only place where sign can change in gimple assignment but they are very specific. Thanks, Kugan

Re: Generating gimple assign stmt that changes sign

Hi Jeff, Thanks for the prompt reply. On 22 May 2018 at 09:10, Jeff Law wrote: > On 05/21/2018 04:50 PM, Kugan Vivekanandarajah wrote: >> Hi, >> >> I am looking to introduce ABSU_EXPR and that would create: >> >> unsigned short res = ABSU_EXPR (short); >>

Sched1 stability issue

away. Is this a known issue? Attached is the sched1 dump snippet where there is the difference. Thanks, Kugan verify found no changes in insn with uid = 41. starting the processing of deferred insns ending the processing of deferred insns df_analyze called Pass 0 for finding pseudo/allocno