Functional Specification for GCC port

hi, What might be functional specifications for a GCC porting project.Output format and ABI might be included in functional specification. For writing a compiler from scratch ,funcional specifications are quite clear ,but for porting GCC what should be included in funcional specification doc

AMD dual core opetron optimization

hi, I'm doing trying to write some optimized code for AMD dual core opetron processor.But things are getting no where.I've installed Fedora 5 with 2.6 series Linux kernel and 4 series GCC Following are few lines of code which are consuming close to 100 cycles.Yes this is not the forum for such

RTL explaination

hi, I'm trying to understand the rtl genrated by gcc for mips processor.I have read gcc internals by Richard Stallman but there are still some confusions in the rtl language. Following is a snippet of code which i'm trying to understand. (insn 9 6 10 (nil) (set (reg:SI 182) (mem/f:SI (sy

Help with following RTL

hi, Following is a c code . int a; main() { a=a+1; } This RTL generated for this programe for mips processor is /***/ ; Function main (note 2 0 3 NOTE_INSN_DELETED) (note 3 2 4 NOTE_INSN_FUNCTION_BEG) (note 4 3 5 NOTE_INSN_DELETED) (note 5

Code Flow for RTL generation

hi, I'm trying to figure out the code flow of gcc.But i'm not been able to locate the location at which an expression is compared with pattern given in .md file. I think .md file is resposible fo generation of emit-insn.c file.But again at which point the functions in emit-insn.c file

Re: Code Flow for RTL generation

is there any way in gdb to step backward. On 6/15/06, Andrew Haley <[EMAIL PROTECTED]> wrote: kernel coder writes: > hi, > I'm trying to figure out the code flow of gcc.But i'm not been > able to locate the location at which an expression is compared with > p

gcc-4.1.0 cross-compile for MIPS

hi, I'm trying to cross compile gcc-4.1.0 for mipsel platform.Following is the sequence of commands which i'm using ../gcc-4.1.0/configure --target=mipsel --without-headres --prefix=/home/shahzad/install/ --with-newlib --enable-languages=c make But following error is generated /home/shahzad

gcc port based on MIPS

hi, I'm trying to port gcc for a processor which is very similar to MIPS.Today i just tried to compile gcc-4.1.0 for this processor by changing configuration files. First i changed the config.sub file in base directory and just added the name of processor ABC. Then i changed the configure.ac file

Re: gcc port based on MIPS

- -- - - - - (define_mode_attr divide_condition [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")]) ;; (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]) As you can see i just omitted the entries of V2SF. On 19 Jun 2006 10:40:45

Re: gcc port based on MIPS

r what the binutils like gas ,ld are called.I know that gcc uses internally the gas and ld to produce final output. But during compilation of gcc ,what role these executables play. On 6/19/06, Andrew Pinski <[EMAIL PROTECTED]> wrote: > > "kernel coder" <[EMAIL

Re: gcc port based on MIPS

e replaced with hard registers and some are assigned stack slots.Is there anything else which happens in this phase.Is above mentioned macro also has something to do with pass. thanks, shahzad On 20 Jun 2006 00:40:07 -0700, Ian Lance Taylor <[EMAIL PROTECTED]> wrote: "kernel coder&q

PIC code in function prologue

hi, I'm having some trouble while understanding the following pic code in function prologue of cris architecture. if (current_function_uses_pic_offset_table) { /* A reference may have been optimized out (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1) so ch

explaination of some gcc functions

hi, I'm trying to understand the backend code of gcc for MIPS architecture.I'm having some trouble while understanding following functions. 1: push_topmost_sequence(); 2: emit_insn_after(seq,get_insns()); 3: pop_topmost_sequence(); 4: emit_insn_before Would you please explain what's the rol

Re: explaination of some gcc functions

ns is being put after the instruction obtained through get_insns() .But does get_insns() also increaments the current instruction pointer.If not then shouldn't the same instruction be emitted in 3). Now again which sequnce is being poped out in 4). On 7/1/06, Eric Christopher <[EMAIL PRO

problem in gcc port based on MIPS

hi, I am trying to write the backend for a processor based on mips.I am facing some problems during compilation of gcc.GAS has been ported for target processor.The store word instruction on ported assembler only supports 16 bit offsets.i.e the only supported format is stw $1,16-bit-offset($2

reduction of GP registers in MIPS backend

hi, I'm trying to learn mips backend by making some changes to it.I just tried to decrease the number of general purpose registers to 25 but following error was generated. dp-bit.c: In function '__muldf3': dp-bit.c:953: error: insn does not satisfy its constraints: (insn 677 231 616 19 dp-bit.c

Re: reduction of GP registers in MIPS backend

This violates an assumption in mips.c:override_options that GPRs come in pairs. Thus you end up with (reg/v:DI 24 $24 [orig:55 res2 ] [55]), which does not satisfy the 'd' constraint. Would you please give a bit more explaination of "GPRs come in pairs" and where this assumption is being checke

Register windows implementation in Xtensa backend

hi, I'm trying to understand the register windows implementation in xtensa backend.I could not find much theory about register windows in extensa.I am trying to understand the register windows implementation by observing the assembly file generated by gcc for a simple c file. Following

segmentation fault in building __floatdisf.o

hi, I'm having some problem during build up of libgcc2 in function __floatdisf(build up of __floatdisf.o).Actually i'm modifying mips backend.The error is ../../gcc-4.1.0/gcc/libgcc2.c: In function '__floatdisf': ../../gcc-4.1.0/gcc/libgcc2.c:1354: internal compiler error: Segmentation fault

Re: segmentation fault in building __floatdisf.o

les. thanks, shaz On 8/30/06, Dave Korn <[EMAIL PROTECTED]> wrote: On 30 August 2006 15:11, kernel coder wrote: > hi, > I'm having some problem during build up of libgcc2 in function > __floatdisf(build up of __floatdisf.o).Actually i'm modifying mips > backend.T

explaination of trampoline

I was just investigating the trampoline implementation.I have defined following macros in machine.h file. #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2) #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode) #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)

Trampoline implementation for MIPS

hi, I'm having some trouble while understanding the generated assembly code for trampoline by mips back-end. Following is the code for which i'm trying to undertsand the generated trampoline code. int foo(int (*f)()){ (*f)(); } main(){ int i; int g(){printf("hello,%d",i);