Preferring offset loads/stores

Dear all, I am working on a GCC port and I have a problem with the code generation for this architecture. Consider this code: void f (int buff[]) { buff[0] += 16; buff[1] += 32; } void g (int buff[]) { buff[0] = 64; buff[1] = 128; } I get this output: : ldw r7,0(r8)

Adding a function call at the beginning

Dear all, I've been trying to add a pass that adds a function call at the beginning of each function. However, my first solution was to simply do something like this: bb = ENTRY_BLOCK_PTR ->next_bb; i = bsi_start (bb); tree call = create_function_call(profile_begin, funcname); bsi_insert_before(&

Re: Adding a function call at the beginning

ame); bsi_insert_before(&i, call, BSI_NEW_STMT); With my basic testing, this does seem to tell GCC to do what I want, Thank you for your help, Jc On Thu, Mar 12, 2009 at 12:38 PM, Sebastian Pop wrote: > Hi JC, > > On Thu, Mar 12, 2009 at 10:58, fearyourself wrote: >> Dea

Reserving a number of consecutive registers

Hi all, My target architecture has an load multiple instruction requiring a certain number of consecutive registers. I've been working on handling this case and trying to convince the local register allocator that he really does want to try to get those consecutive registers for the loads. But hav

Re: Reserving a number of consecutive registers

t you find in find_free_reg. Any comments/suggestions at this point? Thanks a lot, Jc On Fri, Apr 17, 2009 at 2:50 PM, fearyourself wrote: > Hi all, > > My target architecture has an load multiple instruction requiring a > certain number of consecutive registers. I've been worki

Re: Reserving a number of consecutive registers

For the moment, we will be remaining in the 4.3.2 version and have no plans to follow the next 4.4/4.5 versions. Does any architecture do such a "machine-specific reorg" pass. I've looked around and haven't really seen one. Could you give me an idea of where to look and how exactly that would work

Re: Reserving a number of consecutive registers

> The reorg pass runs after register allocation. > You could try to identify consecutive loads within basic blocks, group them That is not too difficult, I've written a pass that checks for that and identifies the loads. - and rename registers or add > copy insns to be able replace them with mul

Re: Reserving a number of consecutive registers

> You should use the DF framework in 4.3.x and later. Ok, I'll try to look at that. Is there an area where I can see how to initialize the framework and get information about which registers are free? Right now, I'm looking in combine.c to see how they are using it. Any insight would be useful,

Expanding a load instruction

Dear all, In the instruction set of my architecture, the offsets of a half-load (HImode) have to be multiples of 2. However, if I set up a structure in a certain way, the compiler will generate: (mem/s/j:HI (plus:DI (reg:DI 134 [ ivtmp.23 ]) (const_int 1 [0x1])) [0 .geno+0 S2 A16]) As th

Reorg and renaming registers

Dear all, I've been working on renaming registers using the DF framework but am wondering if I'm doing things correctly. This is done in the REORG pass because I need to ensure that I have consecutive registers for loads in order to get a load multiple generated. Basically, the beginning of the c

Re: Reorg and renaming registers

code at that point. Thanks again, Jean Christophe Beyler On Thu, Jun 18, 2009 at 12:25 PM, fearyourself wrote: > Dear all, > > I've been working on renaming registers using the DF framework but am > wondering if I'm doing things correctly. This is done in the REORG > pass