gcc4.6.0:combining operate+test

2011-04-12 Thread cirrus75
Hi All, I have been looking at a case in x86 architecture where gcc could generate better code for: if(a+=25) d=c; Insns for operation and test are: (insn 5 2 6 2 (set (reg:SI 62 [ a ]) (mem/c/i:SI (symbol_ref:DI ("a") ) [2 a+0 S4 A32])) test_and.c:9 64 {*movsi_internal}

RE:How to tell IRA to use misaligned DImode load?

2011-04-13 Thread cirrus75
Hi, Do you mean you support unaligned access to any DImode regular type (int64_t) ? regards, Alex Prado "H.J. Lu" wrote: Hi, On my target, SCmode is 4 byte aligned. But to load it into a register, it must be 8byte aligned. I can handle misaligned load in backend. But IRA generates misa

adjacent bitfields optimization

2011-04-25 Thread cirrus75
Hi All, For the fllowing code: typedef struct { int f1:1; int f2:1; int f3:1; int f4:29; } t1; typedef struct { int f1:1; int f2:1; int f3:30; } t2; t1 s1; t2 s2; void func1(void) { s1.f1 = s2.f1; s1.f2 = s2.f2; } we get (x86_64 target): movzbl  s2(%rip), %edx movzbl  s1(%rip),

Re: adjacent bitfields optimization

2011-04-26 Thread cirrus75
Hi, Actually, I would like to ask if all this should be tree level optimization or there would be something to do at backend. I am asking because I am trying to write a new backend. thanks, Alex R. Prado Em 25/04/2011 14:47, Ian Lance Taylor < i...@google.com > escreveu: ci

improving combine pass

2011-04-27 Thread cirrus75
Hi All, I am trying to improve combine pass (for all backends). One approach is changing the order of some insns before combine pass starts. The first problem I have is about the REGNOTES, they need to be rebuilt after changing insn order. Does anyone know how to do that ? Does anyone k

Re: improving combine pass

2011-04-27 Thread cirrus75
. Alex R. Prado Em 27/04/2011 14:43, Ian Lance Taylor < i...@google.com > escreveu: cirrus75 writes: > I am trying to improve combine pass (for all backends). One approach is changing the order of some insns before combine pass starts. The first problem I have is about the REGNOTES,

Re: improving combine pass

2011-04-27 Thread cirrus75
:7 64 {*movsi_internal} (nil)) (insn 9 8 10 2 (set (reg:CCZ 17 flags) (compare:CCZ (reg:SI 61 [ a.2 ]) (const_int 0 [0]))) ../i386_tests/test_and.c:9 2 {*cmpsi_ccno_1} (expr_list:REG_DEAD (reg:SI 61 [ a.2 ]) (nil))) Em 27/04/2011 16:20, Paul Koning < pau

how to specify instruction size for optimization

2010-01-15 Thread cirrus75
Hi, I could not understand exactly how to specify instruction size to gcc (so it can really optimize the code size when -Os is used). I would like to inform gcc that if some registers are used for certain operations, the instruction will be smaller. For example, an add which destination regi