Hi,
I am working on PR105586. This is a -fcompare-debug failure, with the
differences starting during sched1 pass. The sequence of two instructions in a
basic block (block 4) is flipped with -g.
In addition to this, another difference is that an insn is assigned a different
cycle in debug vs non
Hi Richard,
On 27/07/22 12:28 pm, Richard Biener wrote:
> On Tue, Jul 26, 2022 at 8:55 PM Surya Kumari Jangala via Gcc
> wrote:
>> To fix the issue of insns being assigned different cycles, there are two
>> possible solutions:
>>
>> 1. Modify no_real_insns_p()
Hi Vladimir,
I have been analyzing a test case for which shrink wrapping fails
(on powerpc, 64bit LE). But if the same test case is slightly modified,
shrink wrapping kicks in.
Here are the two tests:
Test1 (shrink wrapped)
long
foo (long i, long cond)
{
i = i + 1;
if (cond)
bar ();
r
Hi Richard,
I had submitted a patch for review
(https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631849.html)
regarding scaling save/restore costs of callee save registers with block
frequency in the IRA pass (PR111673).
This patch has been approved by VMakarov
(https://gcc.gnu.org/piperma
Hi Richard,
Ping. Please let me know if the test failure that I mentioned in the mail below
can be handled by changing the expected generated code. I am not conversant
with arm, and hence would appreciate your help.
Regards,
Surya
On 03/11/23 4:58 pm, Surya Kumari Jangala wrote:
> Hi Richard,
>
think.
Regards,
Surya
On 24/11/23 4:18 pm, Richard Earnshaw wrote:
>
>
> On 24/11/2023 08:09, Surya Kumari Jangala via Gcc wrote:
>> Hi Richard,
>> Ping. Please let me know if the test failure that I mentioned in the mail
>> below can be handled by changing the ex
nd is perhaps a little more bomb proof.
>
> I don't really have a strong feeling either way, but perhaps the second is
> slightly preferable.
>
> Richard S: thoughts?
>
> R.
>
>> I believe that this is fine and the test can be modified to allow it to pass
>> o
-save register. With this patch, both the above test gets successfully
shrink wrapped. After committing the patch for PR111673, I plan to get the
LRA fix reviewed.
Please let me know if you need more information.
Regards,
Surya
On 14/12/23 9:41 pm, Richard Earnshaw (lists) wrote:
> On 14/12/2
n :
> set r92, r95 //r92 is assigned x1 and r95 is assigned x0
>
> In BB3, there is a read of x1 after the call
> insn.
> set mem(r92), 0 // r92 is assigned x1
>
> So LRA generates a spill in BB2 after the write to x1.
>
> I have a patch (bootstrapped and regte
Hi Vladimir,
With my patch for PR111673 (scale the spill/restore cost of callee-save
register with the frequency of the entry bb in the routine assign_hard_reg() :
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631849.html), the
following Linaro aarch64 test failed due to an extra 'mov'
Hi Vladimir,
On 14/06/24 10:56 pm, Vladimir Makarov wrote:
>
> On 6/13/24 00:34, Surya Kumari Jangala wrote:
>> Hi Vladimir,
>> With my patch for PR111673 (scale the spill/restore cost of callee-save
>> register with the frequency of the entry bb in the routine assign_hard_reg()
>> :
>> https://
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