Reload Pass

Hi All, Does anyone know of any document describing (in details) the reload phase of GCC? I am planning to write a linear scan reload for GCC (one that does not take reg_renumber but takes instruction specific register allocation and move information). Can anyone point me to some existing code

Re: Reload Pass

ocator and reload, that would probably be doable."? regards, Raj Ian Lance Taylor <[EMAIL PROTECTED]> wrote on 12/21/2006 09:02:04 PM: > Rajkishore Barik <[EMAIL PROTECTED]> writes: > > > Does anyone know of any document describing (in details) the reload phase

Spill cost

Hi, Does anyone know how to obtain the overall spill cost for the old reg alloc of GCC (global.c)? I would like to know the spill cost before reload and after the reload (assuming reload changes the allocation). Are there any interface already available? By spill cost I mean: for each reg i, i

Error help

Checked out a version of new-regalloc code and patched some of my code. It crashes in the bootstrapping part where "xgcc" runs some of my code on __dtor* modules. Is there a way to avoid this bootstrapping? I do not really care about these errors.

coverage mismatch

Hi, I have been trying to use "-fprofile-generate" and "-fprofile-use" for some small bitwise C benchmarks (developed at MIT). I have a check-out of October 2004 GCC build of 4.0 version. It throws me "coverage mismatch error for "arcs"" saying number of counters is "6" instead of "5". How do

combine.c

Can someone tell me why are the "REG_VALUE_PROFILE" notes dropped in "combine.c"? I am using these notes to carry some values to back-end (reg-alloc) and it seems to get lost somewhere. "combine.c" looked to me as the potential place. --Raj

GCC errors

Hi, I am trying to compile MEDIABENCH (@UCLA) using the latest GCC CVS checkout. I get the following errors when I compile with "-O3 -fprofile-generate". I just want to make sure that this is not a silly mistake before I file a bug report. Can someone help? Almost 9 out of 11 benchmarks throw

RTL code

Can someone tell me if there is a way to generate RTL code which does not include use and def of the same pseudo in the same insn? Of course, I can break every such instruction into two but I am wondering if it is already there or anyone has the code already available. i.e. generate t=p56+p76;

spill_failure

Hi, I have been adding some profiling stuff onto the RTL. I get the following error in reload phase. Can someone tell me how to fix this? I use 8th April 2005 check out from CVS. ./mul_mdmd_md.c: In function âmul_mdmd_md_l1_arb_allâ: ./mul_mdmd_md.c:343: error: unable to find a register to spi

Re: spill_failure

> Hmm, let me rephrase your question: > "I did some GCC hacking that I'm not showing, and it doesn't work, > please help me fix it." This is not what I meant. I meant if similar problem has been reported by anyone else before. In any case. This is the piece of code that I add after every integer

Induction Variable

Hi, Can someone tell me how to obtain the following: 1) Given a rtx, find out if it is an induction variable. 2) For an induction variable, find all the loop nest 3) For each loopnest, find the corresponding upper and lower bounds (compile-time) 4) For an induction variables, find the increment/d

-fprofile-arcs

Hi, I am trying to profile the frequency of each basic block of SPEC 2000 benchmarks by compiling them using -fprofile-arcs and opt -O3. After running the benchmark, when I try to read "bb->count" while compiling using "-fbranch-probabilities and -O3", I get "0" values for basic blocks which wer

Re: -fprofile-arcs

The frequencies return "0" using "bb->count". I would like this to reflect "200". How to obtain this information? regards, Raj Jan Hubicka <[EMAIL PROTECTED]> 07/18/2005 10:29 AM To Rajkishore Barik/India/[EMAIL PROTECTED] cc gcc@gcc.gnu.org S

SPECINT 2000 176.gcc compilation

Hi, I am trying to compile SPECINT 2000 176.gcc benchmark using GCC 4.1 April 24th build on Redhat Linux/i386. I get the following error while compiling "reorg.c": reorg.c: In function âfind_end_labelâ: reorg.c:831: error: invalid lvalue in increment reorg.c: In function âdelete_from_delay_slotâ:

Loop information

Can someone please help me getting the following information? 1) I would like to obtain the loop bounds (constant case) of all nested loops of a RTL insn. Is there a data structure over which I can iterate to get bounds for each nested loop of a RTL insn? 2) Is there a way of determining sequen

reload problem in GCC 4.1

Hi, I was trying to feed the "reload" phase with a different hardware register assignment to pseudo registers (using reg_renumber array) than the ones produced by local-alloc or global-alloc. However, I get problems with the following instruction in post-reload.c:391 in "reload_cse_simplify_operan

Re: reload problem in GCC 4.1

The architecture for which I generate code is Intel x86. On 3/6/06, Rajkishore Barik <[EMAIL PROTECTED]> wrote: > Hi, > > I was trying to feed the "reload" phase with a different hardware > register assignment to pseudo registers (using reg_renumber array) > than t

GCC 4.1 on AIX 5.3 POWER 5

Hi All, I am trying to complie GCC 4.1 on an AIX 5.3 machine having 2 power5 processors. I get the following error while trying to compile. Can someone help? "cc" is IBM's xlC compiler. cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-2

replace_rtx

Hi, I am doing some modification to gcc's RTL code. I am trying to split a pseudo (old) into two pseudos (old and new) and rewriting some part of the code to replace the "old" pseudo by the "new" pseudo. I am using the "replace_rtx" function to perform the replacement. However I get "fatal error

Quick Question

Hi, Is there a way to determine if the given RTX is accessing an array element or not? If yes, how do I determine the static size of that array from the given RTX? Thanks a lot in advance. regards, Raj