RTL representation of i386 shrdl instruction is incorrect?

top bits set to 1 instead of moving contents of source into top bits of destination. E.g., when ebx = b72f60d0, ebp = bfcbd2c8 shrdl $16, %ebp, %ebx (ebx is dest, ebp is src) produces 0xd2c8b72f in ebx. But the corresponding RTL produces 0xb72f in ebx. So it seems to me that instead of 'ashiftrt', RTL should have 'lshiftrt'. Can anyone help me with this confusion? -- Thanks, Niranjan Hasabnis, PhD student, Secure Systems Lab, Stony brook University, Stony brook, NY.

Re: RTL representation of i386 shrdl instruction is incorrect?

lying assumption in i386.c guards the bug. On Thu, Jun 5, 2014 at 3:51 AM, Richard Biener wrote: > On Thu, Jun 5, 2014 at 12:03 AM, Niranjan Hasabnis > wrote: >> Hello, >> >> I was studying i386 machine description for my research purpose, >> and I stumbled upon following M

Executing already executed optimization passes again

ny. Please forgive me if this is already answered. -- Thanks, Niranjan Hasabnis, PhD student, Stony brook University.

Re: Executing already executed optimization passes again

r allocation, it's almost too late for anything. > >        paul > > On Mar 18, 2011, at 9:03 PM, Niranjan Hasabnis wrote: > >> Hello, >> >> I'm using GCC plugin to do some analysis and modification on strict-RTL. >> Both things are done after all optim

Testing machine descriptions

bug, what kind of tests are done on it? I'm very much interested in knowing compiler internals and hence this question. Thank you. -- -- Regards, Niranjan Hasabnis.

Re: Testing machine descriptions

ted anyway, which > means running the full dejagnu testsuite before and after your change, > to make sure you didn't break anything. -- -- Regards, Niranjan Hasabnis.

Re: Testing machine descriptions

nt to test, > you'd have to add a target-specific testsuite for them. -- -- Regards, Niranjan Hasabnis.

Re: Testing machine descriptions

Thanks for the info. I will try it out. On Fri, Mar 28, 2014 at 12:07 AM, Senthil Kumar Selvaraj wrote: > On Thu, Mar 27, 2014 at 07:51:06PM -0400, Niranjan Hasabnis wrote: >> Hi DJ Delorie, >> >> Thank you for your answer. It is useful. One more question: so does the >&g

Regarding x86 'sete' instruction and its corresponding RTL

Hello, I'm a student and am currently studying compiler. I was studying GCC's i386 MD, and I found that RTL insn mapped to 'sete' assembly instruction seems to have exactly opposite semantics than 'sete' instruction itself. Below are more details. If someone could clarify the issue, or let me know

Re: Regarding x86 'sete' instruction and its corresponding RTL

27;eq' operator returns STORE_FLAG_VALUE when both >> operands of 'eq' are equal. Otherwise, it returns 0. This is exactly >> opposite of what assembly semantics is. > > No, that's wrong, the semantics of the comparison operators applied to the CC > register have nothing to do with STORE_FLAG_VALUE (see manual section 13.10). > > > Eric Botcazou -- -- Regards, Niranjan Hasabnis.