Problem with memory alignment for 64 byte moves

Hello everyone. I'm porting gcc to a new architecture and I'm allowing use of movdi instructions as the processor allows 8 byte loads. The processor however requires 8 byte loads and stores to be naturally aligned, yet gcc seems to be emitting loads and stores that are 4 byte aligned. How can I ma

Re: Problem with memory alignment for 64 byte moves

split up loads and stores it notices are misaligned? On 3 December 2010 19:34, Ian Lance Taylor wrote: > Neil Hickey writes: > >> I'm porting gcc to a new architecture and I'm allowing use of movdi >> instructions as the processor allows 8 byte loads. The processor >

Question about long jump implementation

I'm trying to implement long jump and I'm using the call instruction in the arm implementation as a reference. The code looks like this: rtx callee, pat; callee = XEXP(operands[0], 0); if (GET_CODE (callee) == SYMBOL_REF ? atdsp_is_long_call_p (SYMBOL_REF_DECL (callee))

Re: Question about long jump implementation

Hi Ian, thanks for the response. I did manage to fix it. The problem was in my call_internal implementation. I went back and looked again at the arm implementation and spotted what I'd done wrong. Sorry for the bother. On 17 December 2010 01:21, Ian Lance Taylor wrote: > Neil Hickey