Le vendredi 11 février 2011 à 13:33 +0100, Bernd Schmidt a écrit :
> Suppose I have two insns, one reserving (A|B|C), and the other reserving
> A. I'm observing that when the first one is scheduled in an otherwise
> empty state, it reserves the A unit and blocks the second one from being
> schedule
Le jeudi 21 octobre 2010 à 21:11 -0700, Ian Lance Taylor a écrit :
> Paul Koning writes:
>
> > To take that example, on the pdp11 an SImode is two HImodes. Could
> > the RTL template in the MD file for, say, addsi3 split that into two
> > or three insns that operate on HImode values and describe
Hi Jon,
Le mardi 26 octobre 2010 à 13:07 +0100, Jon Beniston a écrit :
> What problems do you have building lm32-elf? If you let me know, I can try
> to look in to them.
If you have access to a lm32 toolchain, can you test if
gcc.c-torture/execute/built-in-setjmp.c passes at different optimizatio
Le mardi 07 décembre 2010 à 06:18 -0700, Jeff Law a écrit :
> On 12/06/10 15:07, Ian Lance Taylor wrote:
> Given the two loads don't have a def-use data dependency combine won't
> ever get the opportunity to do anything with them. In general there is
> no pass which combines insns without a true
Le jeudi 06 janvier 2011 à 09:29 -0800, Richard Henderson a écrit :
> On 01/06/2011 06:58 AM, Frederic Riss wrote:
> > 136 is a pseudo. I have movdf and movsf patterns that accepts
> > constants.
>
> This one statement is suspicious to me. Do I read from this that
> you have fp move patterns that
On Thu, 2013-09-12 at 17:39 +0200, Frederic Riss wrote:
> The issue is that I am using super-block
> scheduling in sched2 and that my sched_reorder hook prioritized the
> load operation over the conditional branch that did the alignment
> check.
>
> I'm now leaning toward a scheduler bug (or my cu
Hello,
I'm trying to port a private backend from GCC 4.5 to 4.7, and I'm seeing
some performance degradation in HImode benchmarks. The backend has no
HImode insns apart from the mov and SImode extensions.
I tracked one of the regressions down to the RTL expansion pass. The 4.7
version won't gene
Hi Valdimir
Le vendredi 23 mars 2012 à 12:08 -0400, Vladimir Makarov a écrit :
> Since 4.7 we use more sophisticated trivial coloring criteria which work
> well even on intersected register classes. To be more accurate, we
> calculate an approximation of an profitable hard regs for each pseudo.
