RE: Combined top-down and bottom-up instruction scheduler

. That's why we believe that a hybrid approach might yield good results. We don't have data, for it possibly requires implementing it first. I'd also argue that looking at an OOO pipeline in a steady state is not the only approach. It's also important to consider how quickl

RE: [AArch64] A question about Cortex-A57 pipeline description

Indeed, we observed some problems with scheduling which we believe has more to do with the scheduling algorithm than with the model DFA, as we said in https://gcc.gnu.org/ml/gcc/2015-09/msg00118.html Cheers, -- Evandro Menezes Austin, TX > -Original Mess

[AArch64] Usage of FP regs whe only GP regs are allowed

and restrict the LRA from using FP registers if the user so desires. I still need to come up with a suitable test-case to add, but I'd appreciate any feedback. Thanks, -- Evandro Menezes Austin, USA e.mene...@samsung.com +1-512-425-3365

Loop peeling

to me that it might be safe enough to be implied perhaps at -O3. Is there any reason why this never came into being? Thank you, -- Evandro Menezes Austin, TX

[Aarch64] LRA

It doesn't seem that the option -mno-lra does what it implies. If so, what does it do, for the it does result in differences. TIA Evandro Menezes Austin, TX <mailto:e.mene...@samsung.com> e.mene...@samsung.com +1-512-425-3365

RE: [Aarch64] LRA

That's what I assumed. However, can reload spill GPRs into FPRs as LRA does? For even after specifying -mno-lra, I still see excessive slots in FPRs. Thank you, -- Evandro Menezes Austin, TX > -Original Message- > From: Richard Earnshaw [m

Notes from the BOF on DFP on x86/x86-64 at the GCC Summit

). -- ___ Evandro Menezes AMDAustin, TX

Notes from the BOF on DFP on x86/x86-64 at the GCC Summit

). -- ___ Evandro Menezes AMDAustin, TX