Does GCC support segmented memory ?

I'm porting for a microcontroller which support segment memory. But I don't know how to porting GCC so that it can understand addresses in different memory segment. For example, I want to create seperate code segment and data segment. Is it possible in GCC ? and if the answer is "yes", how can I d

how does GCC support 24 bit addresses on 16 bit targets ?

I'm porting for C166 microcontrollers. It supports 24 bit addresses, but as I know, GCC does not support segmented memory, which is devided into many pages. C166 has four page of addressed, each page has a 16 bit address space. The selection of which page to use is controlled by for DPP register

How to extend lanuage C in GCC ?

I'm porting for a microcontroller. And now I want to add some features to the current language C int GCC (for example some directives such as near, far , ). SO could you please tell me how I can do that ? Thank you very much.

Re: How to extend lanuage C in GCC ?

Yes, things like near, far, .. are all that I need. I think this is the right way for me. I've glanced at the link you gave me. I see that the M32R/D has the attribute "model" with value "small, medium and target", I don't know whether this is the standard atributes for all targets in GCC that I

Re: How to extend lanuage C in GCC ?

Your information is very helpful to me. Thanh you very much. --- Piotr Rak <[EMAIL PROTECTED]> wrote: > Some of them are common, other are target specific. > To add new attribute, you might want take a look at > c_common_attribute_table in gcc/c-common.c, > attribute_spec struct in > gcc/tree.

Where in GCC that allocates the memory for variables ??

I'm porting for a microcontroller with segmented memory. And I want to see how memory are allocated for variables with different directives such as NEAR, FAR . So where can I find it in GCC source code ?

Make error when use SUBTARGET_OVERRIDE_OPTIONS macro

In the file target.c, I declare SUBTARGET_OVERRIDE_OPTIONS to add more command options for my target : -- #ifndef SUBTARGET_OVERRIDE_OPTIONS #define SUBTARGET_OVERRIDE_OPTIONS #endif #define OVERRIDE_OPTIONS

Re: Make error when use SUBTARGET_OVERRIDE_OPTIONS macro

Oh yes, it's my mistake. I've got some grammar mistake in my code, so it didn't run. Thank you . --- Michael Meissner <[EMAIL PROTECTED]> wrote: > On Wed, Nov 12, 2008 at 01:43:50AM -0800, Dong > Phuong wrote: > > > > In the file target.c, I declar

Warning : 'model' attribute directive ignored

I've declared some macros in my target description file to add more attributes to it. When I built it, everything was OK and file cc1.exe was created. But when I use attributes in my C source file. For example : int x __attribute__ ((model ("small))); and use file cc1.exe to compile, there i

How to control code segments ?

I'm porting for a microcontroler which has segmented memory. THe memory is devided into many pages, each page is 16K. And I'm going to use 256 pages for code. But these 256 pages are not continuous in physical memory, so when I want to jump to a function, I have to know what is the segment address

Re: How to control code segments ?

his way > (if I recall correctly). > > It's a little tedious, but not too technically > demanding a solution > > Al Lehotsky > > On Nov 30, 2008, at 2:06 PM, Dong Phuong wrote: > > > I'm porting for a microcontroler which has > segmented > > memo

the rtl expression does not match in define_peephole

I'm defining some peepholes for my machine. But I've got some troubles : I want to use peephole to reduce : ADD R4, 1 CMP R4, a--> CMPD1 R4, a - 1. The assembly code that cc1.exe generates has two instruction : ADD R4, 1 CMP R4, a But when I define peepholes to reduce it, t

the rtl expression does not match in define_peephole

I'm defining some peepholes for my machine. But I've got some troubles : I want to use peephole to reduce : ADD R4, 1 CMP R4, a--> CMPD1 R4, a - 1. The assembly code that cc1.exe generates has two instruction : ADD R4, 1 CMP R4, a But when I define peepholes to reduce it, t