Re: RISC-V maintainer review of glibc patch needed (was: Re: [PATCH] riscv: Remove support for variable page sizes)

LGTM; I believe you are right on both counts that this was borrowed from MIPS and that we do not need this for RISC-V. On Mon, Oct 7, 2019 at 5:21 PM Florian Weimer wrote: > Ping. I need a review of this glibc patch from a RISC-V architecture > maintainer: > >

Re: RISC-V maintainer review of glibc patch needed (was: Re: [PATCH] riscv: Remove support for variable page sizes)

LGTM; I believe you are right on both counts that this was borrowed from MIPS and that we do not need this for RISC-V. On Mon, Oct 7, 2019 at 6:21 PM Florian Weimer wrote: > > Ping. I need a review of this glibc patch from a RISC-V architecture > maintainer: > >

Re: RISC-V port accepted for inclusion in GCC

rt for inclusion in GCC and appointed > Palmer Dabbelt and Andrew Waterman as co-maintainers. > > The patches still require approval by a Global Reviewer, and the > timing to possibly land the patches in GCC 7 need to be coordinated with the > GCC Release Managers. > >

Re: Redundant loads for bitfield accesses

2017 at 4:00 PM, Michael Clark wrote: > ‘cc’ing Andrew Waterman > > I see this comment in SPARC: > > /* Nonzero if access to memory by bytes is slow and undesirable. >For RISC chips, it means that access to memory by bytes is no >better than access by words when possible,

Re: Question regarding riscv_valid_lo_sum_p vs strict-align

IIRC, the reason is that, under strict alignment, it can be assumed that accessing subfields of an aligned datatype won't cross a boundary that would cause the high part to change, thus requiring a different LUI instruction for the subfield access. Under non-strict alignment, this assumption doesn