On Tue, Apr 7, 2009 at 11:03 AM, Ramana Radhakrishnan
wrote:
>> To aid testing, I'd like people to help bootstrapping bootstrappable
>> targets -- arm, alpha, ia64, pa, s390, x86_64.
>
> I'm bootstrapping the branch on an arm-linux-gnueabi target.
bootstrap on
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Ramana Radhakrishnan
> Sent: 08 April 2009 23:30
> To: Paolo Bonzini
> Cc: GCC Development; Ian Lance Taylor; Andreas Krebbel; Uros Bizjak
> Subject: Re: [cond-opta
cpu=cortex-a9 and arch=armv7-a), the Linux kernel (2.6.28.9) and
> rootfs built with this toolchain works fine. But if I build a loadable
> kernel module, when I insmod the module it fails and gives an error as
> "undefined relocation: 43" from the Linux kernel.
This is a binutils question and I just replied to you there.
Ramana
been seeing with
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39929#c12.
Ramana
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Mark Mitchell
> Sent: 06 May 2009 16:10
> To: Richard Earnshaw
> Cc: gcc@gcc.gnu.org
> Subject:
> -Original Message-
> From: Michael Matz [mailto:m...@suse.de]
> Sent: 06 May 2009 18:00
> To: Richard Earnshaw
> Cc: Paolo Bonzini; Joern Rennecke; Ramana Radhakrishnan;
> m...@codesourcery.com; gcc@gcc.gnu.org
> Subject: Re: Setting ARM PIC register (Was: RE: GC
ile for armv4t and why should one have
an additional multi-lib for thumb2 in such a case ?
Cheers
Ramana
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Paolo Bonzini
> Sent: 07 May 2009 14:53
> To: m...@codesourcery.com
> Cc: gcc@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw
> Subject: cond-optab merge delay? [was
was curious if there was a generic template.
Sadly you'd have to keep them in sync with every version of gcc and no
one has thought of maintaining something like that.
Best of luck - HTH
Ramana
>
> graham
>
gle precision calculations.
Only in situations that the user is aware about -ffast-math. I will
point out that single precision floating point operations on NEON are
not completely IEEE compliant.
cheers
Ramana
llowing parameters :
--with-cpu=cortex-a9 --with-fpu=vfpv3-d16 --with-float=softfp
Tests are still running.
Ramana
itialize the
>> + new IV can potentially effects branch optimizations. */
>
> s/effects/effect/
Err I think it should be "affect" rather than effect here.
Thus s/effects/affect
Ramana
ke care of loading this into a
register and then generate equivalent cmp and jmp instructions.
My 2 cents .
HTH
cheers
Ramana
On Thu, 2006-04-13 at 21:17 +0800, Ching-Hua Chang wrote:
> Hi,
> I had wrote doloop_end instruction to support hwloop.
> When try to compile linux kernel, I me
On Thu, 2006-04-13 at 22:37 +0530, Ramana Radhakrishnan wrote:
> Right : A way to work around this would be to hold to not match this
> instruction until reload has been completed and have a define_split to
> convert this to a cmp , bne when its a memory operand matching . Look at
>
/gcc.gnu.org/ml/gcc-patches/2006-01/msg01119.html
It seems to be awaiting review.
cheers
Ramana
ked TARGET_ADDRESS_COST to return 0 always as
well as specifically for POST_INC, POST_DEC and friends , but this did not help
.
Any suggestions would be great ! Thanks for your time .
cheers
Ramana
---
Ramana Radhakrishnan
GNU Tools
Celunite Inc
memcpyreduced.i
Description: Binary d
Hi Zdenek,
I can't seem to reproduce this on 4.1.x with any other port. Maybe I need a sync
up with the latest svn of 4.1.x . I'll try looking at 4.2 head also to spot
differences if any.
Thanks for your time
cheers
Ramana
Ramana Radhakrishnan
GNU Tools
Celunite Inc
On Wed Ju
possible to generate some straightforward heuristic to detect this
> evens (with\without debug info)?
With debug information you could in theory work this out but not
without it especially if LR were used as a temporary.
regards
Ramana
>
> Thank you in advance for any suggestions!
litch and ended up
asking the same question today. Additionally if I use
TARGET_SCHED_SET_SCHED_FLAGS on a port that doesn't use the selective
scheduler, this does nothing. Does anyone know why is this the default
for ports where we don't turn on selective scheduling and might need a
hook to turn this off ?
regards
Ramana
>
> Cheers,
>
> Paulo Matos
>
>
On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov wrote:
> On 11/12/2013, at 5:17 am, Ramana Radhakrishnan
> wrote:
>
>> On Mon, Jul 1, 2013 at 5:31 PM, Paulo Matos wrote:
>>> Hi,
>>>
>>> Near the start of schedule_block, find_modifiable_mems is cal
On Wed, Dec 11, 2013 at 12:02 AM, Maxim Kuvyrkov wrote:
> On 11/12/2013, at 11:14 am, Ramana Radhakrishnan
> wrote:
>
>> On Tue, Dec 10, 2013 at 9:44 PM, Maxim Kuvyrkov wrote:
>>> On 11/12/2013, at 5:17 am, Ramana Radhakrishnan
>>> wrote:
>>>
>&g
k sources since that is where
new development happens.
Thanks,
Ramana
>
>>
>> On 2013/12/28 09:31 AM, Yangfei (Felix) wrote:
>> > Hi,
>> >
>> > I think that simple_return standard pattern is useful for the ARM. I mean
>> it should be good for tar
userspace can't normally disable interrupts.
David
Ramana
) implementation dependent. It is purely a grammar
for the instructions in the assembly language and doesn't attempt to
standardize assembler directives which would have evolved differently
over time and different assemblers. How do you otherwise tell the
assembler whether to assemble for ARM
while IMNSHO.
Adding the warning by default to GAS is just part of the solution.
regards
Ramana
>
> cheers,
> --renato
h this case and I'm guessing that it could
also handle more of the comparison cases and come up with more
intelligent choices and should be made quite a lot more robust than
what it is right now.
regards,
Ramana
diff --git a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c
index ce5eb20..a52953
nd table
is probably worthwhile looking at -
>
> Btw, the canonical case this happens in is probably
>
> for (i = 0; i < n; ++i)
> for (j = 0; j < m && j < i; ++j)
> a[i][j] = ...
>
> thus iterating over the lower/upper triangular part of a non-s
t's triggered this. Would you be
able to experiment with some of the suggestions in that report and
maybe create an equivalent one in the GCC bugzilla .
I haven't had the time to investigate this particular problem further.
regards,
Ramana
>
> I have enabled TARGET_USE_MOVT
you are looking at RTL from a machine description point of view
then you could look at Machine Descriptions in the internals document.
Cheers
Ramana
Cheers
Ramana
On Mon, Mar 10, 2008 at 11:39 AM, Fran Baena <[EMAIL PROTECTED]> wrote:
> Hi all,
>
> RTL represents a low-level langu
locks. I am not clear where one could do this and how to
improve this particular case of code generation. Any suggestions would
be most helpful.
cheers
Ramana
--
Ramana Radhakrishnan
Hi Andrew,
On Mon, Apr 7, 2008 at 4:41 PM, Andrew Pinski <[EMAIL PROTECTED]> wrote:
> On Mon, Apr 7, 2008 at 3:31 AM, Ramana Radhakrishnan <[EMAIL PROTECTED]>
> wrote:
> > The basic case is as explained below.
> >
> > for (i = 0; i < 100; i ++)
&g
Hi Andrew,
I've been looking at doing this possibly in the store sinking pass and
have the following query as below.
On Mon, Apr 7, 2008 at 9:11 PM, Andrew Pinski <[EMAIL PROTECTED]> wrote:
> On Mon, Apr 7, 2008 at 3:31 AM, Ramana Radhakrishnan <[EMAIL PROTECTED]>
> wro
t; converting
>
> if (a > b)
>
> to
>
> cond_1 = a > b;
> if (cond_1)
>
> this way (partial) redundancies can be detected and optimized. Of course
> this may pessimize code in as many cases as it improves it.
Off the top of my head but would so
ively.
HTH.
cheers
Ramana
On Tue, Jul 15, 2008 at 7:50 AM, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
>
> Hello all,
>
> I am not sure if this the right mailing list.
>
> I am involved in the porting of gcc 4.1.2 for a 16 bit target.
> In some cases i noticed that ca
o out of the 16
> available registers ony 5+1+4 registers were used, even though there
> was 6 caller save registers were available
Check your REG_ALLOC_ORDER macro ?
cheers
Ramana
>
>>
>> HTH.
>>
>>
>> cheers
>> Ramana
>>
>> On Tue, Jul 15, 200
,$link
You probably want to see the mt backend for some example as to how to
do it . It looks similar to how we do it in ours.
cheers
Ramana
Ramana Radhakrishnan
Icera Semiconductor
On Wed, Jul 16, 2008 at 12:05 PM, Bingfeng Mei <[EMAIL PROTECTED]> wrote:
> Hello,
> I tried to
and mpfr into our
combined tree. Because this is an embedded port we build with
--disable-shared and that allows gmp and mpfr to automatically get
statically linked into the compiler.
I know that there are many ways to handle this but the point is that
it should work easily and conveniently without extra work.
Ian
--
Ramana Radhakrishnan
lace that the object pointed to also
should also have the same type qualifiers as the pointer being used to
access this.
Thanks in advance
Ramana
--
Ramana Radhakrishnan
Hi Richard,
On 7/10/07, Richard Guenther <[EMAIL PROTECTED]> wrote:
On 7/10/07, Ramana Radhakrishnan <[EMAIL PROTECTED]> wrote:
> Hi,
>
> While upgrading a port of mine to trunk for a testcase I noticed the
> following . Its more of a question for a language lawyer I g
Hi,
Based on this morning's announcement by David at the Steering commitee
panel .
Here's the link to the slides online for folks to look at .
http://www.cse.iitb.ac.in/~uday/gcc-workshop/?file=downloads
--
cheers
Ramana
--
Ramana Radhakrishnan
ugh detail about where
in the function body you are inserting such instrumentation code -
If you are doing such instrumentation in the prologue or epilogue of a
function, you could choose to use gen_reg_rtx to obtain a temporary
register.
So typically obtain a temporary register in the following manner
rtx
if
it is approved.
http://gcc.gnu.org/ml/gcc-patches/2007-09/msg01060.html
The other patch that we have for submission is relatively trivial and
tries to be more precise with size costs for builtins while inlining.
I guess that should be alright for stage3 .
cheers
Ramana
> We are clos
s or manually set this for every
define_insn pattern in your backend.
HTH
cheers
Ramana
--
Ramana Radhakrishnan
/ 4.3
and is not applicable for 4.2.x since the autoincrement detector was
rewritten post 4.2.
http://gcc.gnu.org/ml/gcc-patches/2007-09/msg01060.html
I haven't yet had time to rework this based on the comments but it
surely is on my radar of things to do.
cheers
Ramana
>
>
> Usi
t on busybox mailist, someone advice me to ask here.
You have not mentioned the target platform , the version and other
information so that people can help understand where the problem is .
Please read http://gcc.gnu.org/bugs.html about how to report a bug.
cheers
Ramana
> Thanks very much.
> huamama
>
--
Ramana Radhakrishnan
ugzilla )
Please provide all the information as specified here .
http://gcc.gnu.org/bugs.html#detailed
Thanks
Ramana
> The host platform is cygwin (1.5.24).
> I build the toolchains use buildroot.
> Thanks.
>
>
> On Nov 13, 2007 5:02 PM, Ramana Radhakrishnan <[EMAIL PROTECTED]&
he tree ?
And this is more a question for gcc-help@ rather than gcc@ .
cheers
Ramana
> --thanks, Praveen
>
--
Ramana Radhakrishnan
se is to fake debug information for such to
actually set a breakpoint on the value of the function pointer that
you so set up. I am no DWARF expert but there might be other folks on
the list who might have better ideas about how to implement this.
cheers
Ramana
On Nov 29, 2007 2:27 AM, Mi
hat already.
cheers
Ramana
On Nov 29, 2007 2:27 AM, Michael Meissner <[EMAIL PROTECTED]> wrote:
> One of the things that I've been interested in is adding support to GCC to
> compile individual functions with specific target options. I first presented
> a
> draft at the G
ight preclude my earlier statement.
>
> The idea is to make use of the debugging information as provided by
> the inline-cloner.
All I wanted was the requirement of debug information consistency to
be a part of the proposal for the inline cloner.
cheers
Ramana
>
> > cheers
> > Ramana
>
> Karthik
>
--
Ramana Radhakrishnan
GNU Tools
Celunite Inc.
tp://gcc.gnu.org/wiki/GettingStarted
http://www.cse.iitb.ac.in/~uday/gcc-workshop/?file=downloads
HTH
cheers
Ramana
On Dec 16, 2007 8:24 PM, Hans-Peter Nilsson <[EMAIL PROTECTED]> wrote:
> On Wed, 12 Dec 2007, a2220333 wrote:
>
> > hi,
> > I have been porting tic54x
Hi Balaji,
Its probably better to continue this conversation on gcc@ - so moving
it over there.
On Jan 1, 2008 11:40 AM, Balaji V. Iyer <[EMAIL PROTECTED]> wrote:
> Dear Ramana,
>Thank you very much for your response. I am doing it through
> assembler because I want to
I am pleased to announce that the GCC Steering Committee has appointed
Christophe Lyon as a MVE Reviewer for the AArch32 port.
Please join me in congratulating Christophe on his new role.
Christophe, please update your listings in the MAINTAINERS file.
Regards,
Ramana
congratulating Alex on his new roles. Alex , please
update your listing in the MAINTAINERS file.
Regards
Ramana
mirrors. It has been generated from git commit
> r14-11789-gaa4cd614456de6.
>
> I have so far bootstrapped and tested the release candidate on
> x86_64-linux.
Bootstrap and test with --with-cpu=neoverse-v2 on NVIDIA Grace looks clean.
A similar bootstrap and test run for armv8-a by def
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