Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not support atomic profile update, single mode is
selected
For multi-threaded applications it is quit
On Fri, Nov 04, 2022 at 09:27:34AM +0100, Sebastian Huber wrote:
> Hello,
>
> even recent 32-bit architectures such as RISC-V do not support 64-bit atomic
> operations. Using -fprofile-update=atomic for the 32-bit RISC-V RV32GC ISA
> yields:
>
> warning: target does not support atomic profile up
On 04/11/2022 10:53, Gabriel Paubert wrote:
2. Use
if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED) ==
0)
__atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1, __ATOMIC_RELAXED);
if 32-bit atomics are available.
This assumes little-endian byte order.
Yes, but thi
Hi!
On 2022-10-20T13:34:41+0200, Jakub Jelinek via Gcc-patches
wrote:
> we'll need to update the offloading wiki
I'll look into that. I assume we just remove any "Intel MIC" text,
unless historically or otherwise still relevant, of course.
Likewise I'll look through open PRs to see if any can
On Fri, Nov 04, 2022 at 11:05:13AM +0100, Thomas Schwinge wrote:
> Hi!
>
> On 2022-10-20T13:34:41+0200, Jakub Jelinek via Gcc-patches
> wrote:
> > we'll need to update the offloading wiki
>
> I'll look into that. I assume we just remove any "Intel MIC" text,
> unless historically or otherwise
On 03/11/2022 16:19, Michael Matz via Gcc wrote:
Hello,
On Thu, 3 Nov 2022, Florian Weimer via Gcc wrote:
will not have propagated widely once GCC 13 releases, so rejecting
implicit ints in GCC 13 might be too early. GCC 14 might want to switch
to C23/C24 mode by default, activating auto supp
Snapshot gcc-11-20221104 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/11-20221104/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 11 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
Hi Jakub,
I had a question about the aforementioned commit in RV backend.
(define_split
[(set (match_operand:GPR 0 "register_operand")
(and:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "p2m1_shift_operand")))
+ (clobber (match_operand:GPR 3 "regist
On 11/4/22 16:59, Vineet Gupta wrote:
Hi Jakub,
I had a question about the aforementioned commit in RV backend.
(define_split
[(set (match_operand:GPR 0 "register_operand")
(and:GPR (match_operand:GPR 1 "register_operand")
(match_operand:GPR 2 "p2m1_shift_operand")))
+
On 11/4/22 16:13, Jeff Law wrote:
On 11/4/22 16:59, Vineet Gupta wrote:
Hi Jakub,
I had a question about the aforementioned commit in RV backend.
(define_split
[(set (match_operand:GPR 0 "register_operand")
(and:GPR (match_operand:GPR 1 "register_operand")
(match_operand:
On 11/4/22 17:38, Vineet Gupta wrote:
commit 666fdc46bc848984ee7d2906f2dfe10e1ee5d535
Author: Jim Wilson
Date: Sat Jun 30 21:52:01 2018 +
RISC-V: Add patterns to convert AND mask to two shifts.
gcc/
* config/riscv/predicates.md (p2m1_shift_operand): New.
On Monday 31 October 2022 10:55:59 Jan Beulich wrote:
> On 30.10.2022 02:06, Pali Rohár via Binutils wrote:
> > * GCC or LD (not sure who) sets memory alignment characteristics
> > (IMAGE_SCN_ALIGN_MASK) into the sections of PE executable binary.
> > These characteristics should be only in COFF
On Saturday 05 November 2022 01:57:49 Pali Rohár wrote:
> On Monday 31 October 2022 10:55:59 Jan Beulich wrote:
> > On 30.10.2022 02:06, Pali Rohár via Binutils wrote:
> > > * GCC or LD (not sure who) sets memory alignment characteristics
> > > (IMAGE_SCN_ALIGN_MASK) into the sections of PE execu
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