On Tue, Aug 20, 2019 at 08:56:39AM +0200, Richard Biener wrote:
> Most of these suggestions involve adding some sort of virtual registers
> So I hacked the machine description to add two new registers Z1 and Z2
> with the same mode as X and Y.
>
> Obviously the assembler b
On Tue, Aug 20, 2019 at 9:07 AM John Darrington
wrote:
>
> On Tue, Aug 20, 2019 at 08:56:39AM +0200, Richard Biener wrote:
>
> > Most of these suggestions involve adding some sort of virtual registers
> > So I hacked the machine description to add two new registers Z1 and Z2
> > wit
Tejas: given the controversy, I agree unspecs sound like a good approach
for now. We can always go back and add the rtx codes later once there's
agreement on what they should look like.
Segher Boessenkool writes:
> On Sat, Aug 17, 2019 at 09:21:00AM +0100, Richard Sandiford wrote:
>> Tejas Joshi
Hi,
calculated sha512 of *gcc-9.2.0.tar.gz* is:
55fead9cac2374b18134c17a143fc9317f67be834589303d31a7c3a6878e6bef22a0590fda902a07cb60f802df035e67975a8ab6a641048e0baa89af439a46ca
but it's reported as:
a916970e1d02c218d913744b171be5123475e2a31179812297c6812e93a6535eaf6aea0a52e0d5b0b6eb47410921d08306
On Tue, Aug 20, 2019 at 08:41:29AM +0100, Richard Sandiford wrote:
> Tejas: given the controversy, I agree unspecs sound like a good approach
> for now. We can always go back and add the rtx codes later once there's
> agreement on what they should look like.
Yup.
> Segher Boessenkool writes:
>
Segher Boessenkool writes:
>> > And yes, various parts of GCC can manipulate RTL, doing substitution and
>> > algebraic simplication and whatnot. All within the rules of RTL. And
>> > that means nothing ever can "pass" a float_narrow, because there are no
>> > rules that allow it to.
>>
>> You
On Tue, Aug 20, 2019 at 12:34 PM Andrea Carretti Mambrini
wrote:
>
> Hi,
> calculated sha512 of *gcc-9.2.0.tar.gz* is:
> 55fead9cac2374b18134c17a143fc9317f67be834589303d31a7c3a6878e6bef22a0590fda902a07cb60f802df035e67975a8ab6a641048e0baa89af439a46ca
>
> but it's reported as:
> a916970e1d02c218d913
On Tue, Aug 20, 2019 at 01:59:06PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> >> [(set (match_operand:SI 0 "register_operand" "=d")
> >> (truncate:SI
> >> (lshiftrt:DI
> >
> > (this is optimised to a subreg, in many cases, for example).
>
> Right. MIPS avoi
Segher Boessenkool writes:
> On Tue, Aug 20, 2019 at 01:59:06PM +0100, Richard Sandiford wrote:
>> Segher Boessenkool writes:
>> >> [(set (match_operand:SI 0 "register_operand" "=d")
>> >> (truncate:SI
>> >> (lshiftrt:DI
>> >
>> > (this is optimised to a subreg, in many cases,
Richard Sandiford writes:
>> And yes, it is icky. But it is sound, as far as I can see.
>
> I really disagree that it's sound, but no point me saying why again :-)
>
> (It could certainly be made to work with sufficient hacks of course,
> like pretty much anything could, but I don't think that's
On 7/26/19 6:03 AM, Iain Sandoe wrote:
Hello Sebastian,
On 26 Jul 2019, at 10:19, Florian Weimer wrote:
C++ coroutines are stackless. I don't think any new low-level run-time
support will be needed.
correct, C++20 coroutines and threading mechanisms are orthogonal
facilities; one can use
On August 20, 2019 5:19:33 PM GMT+02:00, Nathan Sidwell wrote:
>On 7/26/19 6:03 AM, Iain Sandoe wrote:
>> Hello Sebastian,
>>
>>> On 26 Jul 2019, at 10:19, Florian Weimer wrote:
>
>>> C++ coroutines are stackless. I don't think any new low-level
>run-time
>>> support will be needed.
>>
>> corr
On Tue, 20 Aug 2019, Segher Boessenkool wrote:
> plus minus neg mult div mod smin smax abs sqrt fma I think? And let's
> hope we never ever have to do saturating versions of FP :-)
There are six operations with narrowing versions in TS 18661-1 (plus minus
mult div sqrt fma).
neg and abs are o
* Richard Biener:
> On August 20, 2019 5:19:33 PM GMT+02:00, Nathan Sidwell
> wrote:
>>On 7/26/19 6:03 AM, Iain Sandoe wrote:
>>> Hello Sebastian,
>>>
On 26 Jul 2019, at 10:19, Florian Weimer wrote:
>>
C++ coroutines are stackless. I don't think any new low-level
>>run-time
sup
On Tue, Aug 20, 2019 at 03:43:43PM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > On Tue, Aug 20, 2019 at 01:59:06PM +0100, Richard Sandiford wrote:
> >> Segher Boessenkool writes:
> >> >> [(set (match_operand:SI 0 "register_operand" "=d")
> >> >> (truncate:SI
> >> >>
I wrote:
Committed as r274551.
Well, this revision appears to have woken quite a few bugs from their
slumber. While argument mismatch was always illegal, it seems to have
been a common idiom at one time. And, like almost all bad habits of
the past, SPEC also has this (see PR 91473, where you
On Tue, Aug 20, 2019 at 09:56:27PM +0200, Thomas Koenig wrote:
> I wrote:
>
> > Committed as r274551.
>
> Well, this revision appears to have woken quite a few bugs from their
> slumber. While argument mismatch was always illegal, it seems to have
> been a common idiom at one time. And, like al
On Aug 20 2019, Steve Kargl wrote:
On Tue, Aug 20, 2019 at 09:56:27PM +0200, Thomas Koenig wrote:
I wrote:
> Committed as r274551.
Well, this revision appears to have woken quite a few bugs from their
slumber. While argument mismatch was always illegal, it seems to have
been a common idiom at
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