Ryan Burn writes:
> Is there any way to easily build a stage1 gcc with macro support for
> debugging?
Set STAGE1_CFLAGS.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
On Thu, Dec 3, 2015 at 8:54 AM, Uday P. Khedker wrote:
> We are implementing points-to analysis in GCC 4.7.2 and need to distinguish
> between
> pointers to scalars and the pointers to structures. This distinction by
> using the TYPE (TREE_TYPE)
> hierarchy of the tree node of the pointer. We have
> On Dec 3, 2015, at 12:29 AM, Bernd Edlinger wrote:
>
>> ...
>> If the goal is to order things wrt x, why wouldn't you just reference x?
>>
>> x = 1;
>> asm volatile("nop":"+m"(x));
>> x = 0;
>>
>
> Exactly, that is what I mean. Either the asm can use memory clobber
> or it can use ou
On 12/02/2015 06:48 PM, Peter Bergner wrote:
On Wed, 2015-12-02 at 20:05 -0500, Ryan Burn wrote:
Is there any way to easily build a stage1 gcc with macro support for debugging?
I tried setting CFLAGS, and CXXFLAGS to specify "-O0 -g3" via the
command line before running configure, but that only
Can the instruction scheduler actually rewrite instructions? I didn't
think so but when I compile some code on MIPS with:
-O2 -fno-ivopts -fno-peephole2 -fno-schedule-insns2
I get:
$L4:
lbu $3,0($4)
addiu $4,$4,1
lbu $2,0($5)
beq $3,$0,$L7
On Thu, Dec 3, 2015 at 7:01 PM, Steve Ellcey wrote:
> Can the instruction scheduler actually rewrite instructions? I didn't
> think so but when I compile some code on MIPS with:
>
> -O2 -fno-ivopts -fno-peephole2 -fno-schedule-insns2
>
> I get:
>
> $L4:
> lbu $3,0($4)
>
Am 03.12.2015 um 16:24 schrieb paul_kon...@dell.com:
> On the other hand, asm volatile ("foo":::) has a different meaning.
> That specifically says that "foo" doesn't clobber anything.
Well, not exactly, see the md_asm_adjust target callback.
On i386, rs6000, visium, cris and mn10300 targets
Given a combination of "I have new responsibilities" and "nothing has
happened with mep for a long time" I would like to step down as mep
maintainer.
If someone would like to pick up maintainership of this target, please
contact me and/or the steering committee. Otherwise, I propose this
target
On Thu, 2015-12-03 at 19:56 +, Ramana Radhakrishnan wrote:
> IIRC it's because the scheduler *thinks* it can get a tighter schedule
> - probably because it thinks it can dual issue the lbu from $4 and the
> addiu to $5. Can it think so ? This may be related -
> https://gcc.gnu.org/ml/gcc-patch
On Wed, Dec 2, 2015 at 5:11 AM, Steve Ellcey wrote:
>
> I have a question involving ivopts and PR 48814, which was a fix for
> the post increment operation. Prior to the fix for PR 48814, MIPS
> would generate this loop for strcmp (C code from glibc):
>
> $L4:
> lbu $3,0($4)
>
On Fri, Dec 4, 2015 at 10:48 AM, Bin.Cheng wrote:
> On Wed, Dec 2, 2015 at 5:11 AM, Steve Ellcey wrote:
>>
>> I have a question involving ivopts and PR 48814, which was a fix for
>> the post increment operation. Prior to the fix for PR 48814, MIPS
>> would generate this loop for strcmp (C code f
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