[ANN] C++Now 2014: 5 Days to Submissions Deadline

Hi, Only 5 days left before the submissions deadline for C++Now 2014! C++Now is a general C++ conference for C++ experts and enthusiasts. It is not specific to any library/framework or compiler vendor and has three tracks with presentations ranging from hands-on, practical tutorials to advanced C

Rust front-end to GCC

Hey all Some of you may have noticed the gccrs branch on the git mirror. Since PyCon IE 2013 i gave a talk on my Python Front-end pet project and heard about rust by a few people and i never really looked at it before until then but i've kind of been hooked since. So to learn the language i've be

Re: [rust-dev] Rust front-end to GCC

On Tue, Dec 3, 2013 at 12:22 PM, Philip Herron wrote: > Hey all > > Some of you may have noticed the gccrs branch on the git mirror. Since PyCon > IE 2013 i gave a talk on my Python Front-end pet project and heard about > rust by a few people and i never really looked at it before until then but >

Truncate optimisation question

Hi all, I'm investigating a testsuite failure on arm: gcc.target/arm/unsigned-extend-1.c For code: unsigned char foo (unsigned char c) { return (c >= '0') && (c <= '9'); } we end up generating: sub r0, r0, #48 uxtbr0, r0 cmp r0, #9 movhi r0, #0

Re: Truncate optimisation question

> For code: > > unsigned char foo (unsigned char c) > { >return (c >= '0') && (c <= '9'); > } > > we end up generating: > > sub r0, r0, #48 > uxtbr0, r0 > cmp r0, #9 > movhi r0, #0 > movls r0, #1 > bx lr > > The extr

Re: Truncate optimisation question

Eric Botcazou writes: >> For code: >> >> unsigned char foo (unsigned char c) >> { >>return (c >= '0') && (c <= '9'); >> } >> >> we end up generating: >> >> sub r0, r0, #48 >> uxtbr0, r0 >> cmp r0, #9 >> movhi r0, #0 >> movls r0, #

Re: Truncate optimisation question

Eric Botcazou wrote: >> For code: >> >> unsigned char foo (unsigned char c) >> { >>return (c >= '0') && (c <= '9'); >> } >> >> we end up generating: >> >> sub r0, r0, #48 >> uxtbr0, r0 >> cmp r0, #9 >> movhi r0, #0 >> movls r0, #1

Appointment as SLSR maintainer

Sorry for the delay on this, it fell off my radar as we wrapped up stage1 development. -- I am pleased to announce that the GCC Steering Committee has accepted you as the maintainer for the SLSR optimization pass. Please update your listing in the MAINTAINERS file and congratulations on

Re: Truncate optimisation question

> I don't think this is the way to go. AIUI the problem here isn't that > RISC architectures don't have QImode adds as such. If we were going > to combine insn 6 and insn 7 _in isolation_ then we would have either: > >(zero_extend:SI (subreg:QI (plus:SI (subreg:QI (reg:SI R)) >

Re: Truncate optimisation question

> To me promote_mode sounds like the best fit. But doesn't combine do > instruction validation? So in this case the target claims to support the > narrow operation? Part of the problem is that it's not in the combiner, it's in simplify-rtx.c, so it's applied liberally when you're manipulating th

Re: Truncate optimisation question

Eric Botcazou writes: >> I don't think this is the way to go. AIUI the problem here isn't that >> RISC architectures don't have QImode adds as such. If we were going >> to combine insn 6 and insn 7 _in isolation_ then we would have either: >> >>(zero_extend:SI (subreg:QI (plus:SI (subreg:QI