2011/3/20 Georg-Johann Lay :
> The AVR controller basically has two kinds of hard registers:
>
> * LD_REGS (constraint "d") that can move immediates
> * NO_LD_REGS (constraint "l") that cannot move immediates
>
> movsi insn of avr backend does not supply an "l,i" constraint alternative,
> so that r
Hi,
On Sun, 20 Mar 2011, H.J. Lu wrote:
> I don't think it will help x32 and I think it will make it harder to add
> x32 support. I still want to see a real usage before I add it.
% cat real-world.c
/* intptr_t; what's that? */
union space_saving_htab_element {
void *generic_pointer;
/* Usu
On Mon, Mar 21, 2011 at 1:20 AM, Michael Matz wrote:
> Hi,
>
> On Sun, 20 Mar 2011, H.J. Lu wrote:
>
>> I don't think it will help x32 and I think it will make it harder to add
>> x32 support. I still want to see a real usage before I add it.
>
> % cat real-world.c
> /* intptr_t; what's that? */
>
Denis Chertykov schrieb:
> 2011/3/20 Georg-Johann Lay :
>> The AVR controller basically has two kinds of hard registers:
>>
>> * LD_REGS (constraint "d") that can move immediates
>> * NO_LD_REGS (constraint "l") that cannot move immediates
>>
>> movsi insn of avr backend does not supply an "l,i" co
2011/3/21 Georg-Johann Lay :
> Denis Chertykov schrieb:
>> 2011/3/20 Georg-Johann Lay :
>>> The AVR controller basically has two kinds of hard registers:
>>>
>>> * LD_REGS (constraint "d") that can move immediates
>>> * NO_LD_REGS (constraint "l") that cannot move immediates
>>>
>>> movsi insn of a
The toplevel config-ml.in configure fragment has some code for a few
targets that allows modifying the set of multilibs built, based on
configure options, to be different from that given by $CC -print-multi-lib.
The options in question are described in GCC's install.texi (but the
lists there may
On Mon, 2011-03-21 at 14:36 +, Joseph S. Myers wrote:
> Some targets provide finer-grained control over which multilibs are
> built
> (e.g., @option{--disable-softfloat}):
> @table @code
> @item arm-*-*
> fpu, 26bit, underscore, interwork, biendian, nofmult.
I'd expect that code to
Richard Earnshaw writes:
> On Mon, 2011-03-21 at 14:36 +, Joseph S. Myers wrote:
>> Some targets provide finer-grained control over which multilibs are
>> built
>> (e.g., @option{--disable-softfloat}):
>> @table @code
>> @item arm-*-*
>> fpu, 26bit, underscore, interwork, biendian,
> In particular, isn't it a known issue that 32-bit hosts and 64-bit hosts can
> generate different constant-loading sequences owing to the differing size of
> HOST_WIDE_INT?
>
> Was that 32-bit Solaris?
>
> cheers,
> DaveK
As a followup, I built a 32-bit version of the entire toolchain and it pro
Denis Chertykov schrieb:
>
Please, provide test results.
Denis.
Ok, will take some time.
Johann
"H.J. Lu" writes:
> [...]
> GCC git mirror hasn't been updated for more than 30 hours.
git svn fetch was blocked on a "index mismatch: ..." error,
apparently necessitating a full git-svn metadata rebuild. It
should be done in a few more hours. Darn fragile thing, git-svn.
- FChE
"Joseph S. Myers" writes:
> @item mips*-*-*
> single-float, biendian, softfloat.
FWIW, I've no objection from a MIPS point of view. Like Richard was
saying for ARM, single-float has long since stopped working for MIPS,
because no target has single-float multilibs.
Richard
I knew that doing transformations at earlier stage would be cleaner solution.
But, due to some reason, I'm not able to do it at earlier stages.
But I was thinking that some optimizations such as CSE, loop optimizations,
should be reusable, and hence was exploring the idea of using them after my
tr
A second GCC 4.6.0 release candidate is available at:
ftp://gcc.gnu.org/pub/gcc/snapshots/4.6.0-RC-20110321/
Please test the tarballs and report any problems to Bugzilla.
CC me on the bugs if you believe they are regressions from
previous releases severe enough to block the 4.6.0 release.
If no
roy rosen writes:
> 2010/10/26 Ian Lance Taylor :
>> roy rosen writes:
>>
>>> I am trying to demonstrate my port capabilities.
>>> I am writing an application which needs to use instructions like max
>>> a,b,c,d,e,f where a,b,c are inputs and d,e,f are outputs.
>>> Is that possible to write an i
Hello All,
I have a question regarding PowerPC64 bit ABI. Since GCC generates FP
instructions for Non FP code, i was running in to issues with
applications having interrupts (i have seen some threads with people
complaining about this). So the other option to resolve this was to
build the entire a
On Mon, Mar 21, 2011 at 10:50 PM, Rohit Arul Raj wrote:
> Hello All,
>
> I have a question regarding PowerPC64 bit ABI. Since GCC generates FP
> instructions for Non FP code, i was running in to issues with
> applications having interrupts (i have seen some threads with people
> complaining about
Hello Andrew,
On Tue, Mar 22, 2011 at 11:41 AM, Andrew Pinski wrote:
> On Mon, Mar 21, 2011 at 10:50 PM, Rohit Arul Raj
> wrote:
>> Hello All,
>>
>> I have a question regarding PowerPC64 bit ABI. Since GCC generates FP
>> instructions for Non FP code, i was running in to issues with
>> applicat
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