Thanx,
this paper is helpful and shows what I expected. But I still have a
problem about va-argument-passing. The MS compiler reserves stack space
for all may va-callable methods register arguments. So far, good. This
means for GCC setting up REG_PARM_STACK_SPACE to the value of a stack
argum
[EMAIL PROTECTED] wrote on 26/02/2007 10:40:59:
>I am targeting GCC 4.1.1 to a custom RISC processor; which has some vector
>instructions (32 bit vectors). It can perform two 16 bit/ or four 8 bit
>additions, subtractions, multiplications & shift operations
simultaneously.
>I would like to use t
Hello,
thanks for reply. I was reading and comparing machine description files
from other backends. Now I am using a template like this:
---snip---
(define_insn "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (mem:QI (match_operand:QI 1 sym_ref_mem_operand"
""))
Hi.
These days I began to get spam in my mail box.
I found, that my mail address ([EMAIL PROTECTED]) is published on :
http://gcc.gnu.org/ml/gcc/2006-08/msg00227.html
Please, remove it from there, thanks.
> The patterns clobber and use the rs6000 link register as a match_scratch
> with constraint of the link register class:
>
>(clobber (match_scratch:SI 0 "=l"))
>
> instead of clobbering the link register hard register directly in the
> early insn generation. This style dates to the original
Hello,
> I've been trying to keep the GCC_4.3_Release_Planning wiki page up to
> date, and I'd like to be sure I haven't missed anything going in. I've
> moved several projects to the Completed section, and if I've done
> anything in error there, please correct it.
>
> So here's a survey of what'
H. J. Lu wrote:
We are working on complete data of SPEC CPU 2K/2006 on Core 2 Duo.
It will take about a week.
There are results' comparison I got for gcc 4.2 revisions 117890,
117891 and 121952 on SPEC CPU2K/2006
SPEC CPU2000:
117891 vs 117890 121952 vs 117890
164.gzip
Hello,
I appreciate it if someone could tell me how I can create a -0 RTX
expression (like CONST0_RTX)?
Thanks,
Revital
Alexander wrote:
Hi.
These days I began to get spam in my mail box.
I found, that my mail address ([EMAIL PROTECTED]) is published on :
http://gcc.gnu.org/ml/gcc/2006-08/msg00227.html
Please, remove it from there, thanks.
And now it is here also:
http://gcc.gnu.org/ml/gcc/2007-02/msg00606.html
On Mon, Feb 26, 2007 at 09:40:59AM +0100, Kai Tietz wrote:
> So is there allready a mechanism in gcc, by whom I can reserve for all
> methods simple space on stack for the 4 used register parameters, even if
> they are not used for argument passing ?
See sparc.h.
r~
> > Do you remember why you wrote the call patterns this way? Was
> > there a problem with reload and clobbers of hard registers in a register
> > class containing a single register or some other historical quirk?
>
> I think the former. I no longer remember the details, but if you had
> a clobb
[ gcc -> gcc-patches ]
Dominique,
thanks a lot for your patch. I have tested this on i686-suse-linux,
comparing the output of contrib/test_installed both before and after
your patch and committed it with the following ChangeLog entry:
2007-02-26 Dominique Dhumieres <[EMAIL PROTECTED]>
I am looking at PR target/30826 (an IA64 ABI bug) and have come up with
a patch that basically involves turning off the
CALL_EXPR_RETURN_SLOT_OPT optimization in some instances and forcing GCC
to create a temporary for the (large aggragete) return value of a
function and then copying that temporar
Snapshot gcc-4.1-20070226 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.1-20070226/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.1 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
Kai Tietz writes:
>But I still have a problem about va-argument-passing. The MS compiler
>reserves stack space for all may va-callable methods register arguments.
Passing arguments to functions with variable arguments isn't a special
case here. According to Microsoft's documentation, you always n
On Mon, Feb 26, 2007 at 02:04:36PM -0800, Steve Ellcey wrote:
> I am looking at PR target/30826 (an IA64 ABI bug) and have come up with
> a patch that basically involves turning off the
> CALL_EXPR_RETURN_SLOT_OPT optimization in some instances and forcing GCC
> to create a temporary for the (large
> Actually, this depended on SMALL_REGISTER_CLASSES. If the target was not
> marked has having SMALL_REGISTER_CLASSES, any explicitly used hard register
> would not be used for register and/or spill allocations anywhere in the
> function.
That's one issue, but I'm not sure is the only one. Also
Hi,
-march=native choose pentium4 instead of pentium-m for Pentium M processors
(see config/i386/driver-i386.c)? Is this intentional or a typo?
--
Zuxy
Alexandre Tzannes <[EMAIL PROTECTED]> writes:
> I'm Alex Tzannes and I am porting GCC 4.0.2 to a new experimental parallel
> architecture. Here's one issue I don't know how to go about. The ISA of
> our machine is based on MIPS (so I made a copy of the MIPS back end and
> have been modifying that)
"Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> /* { dg-final { scan-tree-dump "b4 = 6.3e+1" "gimple" } } */
Note that scan-tree-dump takes a regular expression. So you are
looking for '6' followed by any character followed by '3' followed by
one or more 'e's followed by '1'.
Ian
Revital1 Eres <[EMAIL PROTECTED]> writes:
> I appreciate it if someone could tell me how I can create a -0 RTX
> expression (like CONST0_RTX)?
The easy way is something along the lines of:
simplify_gen_unary (NEG, mode, CONST0_RTX (mode), mode)
Ian
Zuxy Meng wrote:
Hi,
-march=native choose pentium4 instead of pentium-m for Pentium M processors
(see config/i386/driver-i386.c)? Is this intentional or a typo?
I think the reason is that Intel changed completely the
microarchitecture (going back to something that actually is more similar
t
On Tue, Feb 27, 2007 at 12:30:16PM +0800, Zuxy Meng wrote:
> Hi,
>
> -march=native choose pentium4 instead of pentium-m for Pentium M processors
> (see config/i386/driver-i386.c)? Is this intentional or a typo?
>
It is because Pentium M implements Pentium instructions. You should
get:
bash-3.0
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