2007/10/11, Jim Wilson <[EMAIL PROTECTED]>:
Thanks for you helpful hints ! And I am sorry for such a late reply.
I have figured out this problem yesterday :-).
> Do we know for sure that the scheduler is failing here? Have you looked
> at -da RTL dumps to verify which pass is performing the inco
ÎâêØ wrote:
Well... Is there anything I miss or forget to do ?
Someone needs to step through code in a debugger and try to figure out
what is going wrong.
I made an initial attempt at that. I hacked gcc a little to try to
force a failure with a contrived testcase. The first thing I notice
"rws_access_reg should be handling this correctly. It uses
HARD_REGNO_NREGS to get the number of regs referred to by a reg rtl.
So it should return 64 in this case, and then it will iterate over all
64-bit PR regs when checking for a dependency."
I have found HARD_REGNO_NREGS in ia64.h
#define HA
Ô¬Á¢Íþ wrote:
So, my question becomes clear:
How to solve this problem by making GCC knows the data dependencies
between mov X = pr (or mov pr = X, -1) and other usage of a specific
predicate register (e.g. p6, p7)?
We already have support for these move instructions. See the
movdi_internal p
Hi,
I'm working on IA64 with GCC-4.1.1; what I do is to instrument some
sensitive instructions (e.g. memory access) to do information flow
tracking. As I insert the instrumentation after register allocation,
I need to allocate general registers and predicates myself; for
corner cases in allocatio
Hi,
I'm working on IA64 with GCC-4.1.1; what I do is to instrument some
sensitive instructions (e.g. memory access) to do information flow
tracking. As I insert the instrumentation after register allocation,
I need to allocate general registers and predicates myself; for
corner cases in allocatio
