On 02/09/2011 08:27 AM, Hans-Peter Nilsson wrote:
> On Fri, 28 Jan 2011, Jean-Marc Saffroy wrote:
>> (define_constraint "I"
>> "Signed 6-bit integer constant for binops."
>> (and (match_code "const_int")
>>(match_test "IN_RANGE (ival, -24, 32)")))
>>
>> (define_register_constraint "A" "
On Fri, 28 Jan 2011, Jean-Marc Saffroy wrote:
> (define_constraint "I"
> "Signed 6-bit integer constant for binops."
> (and (match_code "const_int")
>(match_test "IN_RANGE (ival, -24, 32)")))
>
> (define_register_constraint "A" "ADDR_REGS"
> "The address registers.")
>
> (define_regis
Jean-Marc Saffroy writes:
> So it seems I will have to have adddi3 be a define_expand that splits
> the increment by N into smaller increments when called with
> (reload_in_progress||reload_completed). Does that sound reasonable?
Yes.
Ian
On 01/28/2011 09:45 PM, Ian Lance Taylor wrote:
> Jean-Marc Saffroy writes:
>
>> On 01/28/2011 06:44 PM, Ian Lance Taylor wrote:
>>> Jean-Marc Saffroy writes:
>>>
error: insn does not satisfy its constraints:
(insn 1424 1423 141 (set (reg:DI 2 r2)
(plus:DI (reg:DI 2 r2)
>>
Jean-Marc Saffroy writes:
> On 01/28/2011 06:44 PM, Ian Lance Taylor wrote:
>> Jean-Marc Saffroy writes:
>>
>>> error: insn does not satisfy its constraints:
>>> (insn 1424 1423 141 (set (reg:DI 2 r2)
>>> (plus:DI (reg:DI 2 r2)
>>> (const_int 40 [0x28])))
>>> /home/jmsaffroy
On 01/28/2011 06:44 PM, Ian Lance Taylor wrote:
> Jean-Marc Saffroy writes:
>
>> error: insn does not satisfy its constraints:
>> (insn 1424 1423 141 (set (reg:DI 2 r2)
>> (plus:DI (reg:DI 2 r2)
>> (const_int 40 [0x28])))
>> /home/jmsaffroy/cygnus/src/newlib/libc/time/strptime
Jean-Marc Saffroy writes:
> error: insn does not satisfy its constraints:
> (insn 1424 1423 141 (set (reg:DI 2 r2)
> (plus:DI (reg:DI 2 r2)
> (const_int 40 [0x28])))
> /home/jmsaffroy/cygnus/src/newlib/libc/time/strptime.c:165 24 {adddi3}
> (expr_list:REG_EQUIV (plus:DI (
Hi gcc gurus,
I'm trying to port GCC to a new architecture, I'm new to gcc, and have
little problems defining add correctly.
My target has 2 types of (DI mode) registers, so I defined 2 classes:
- class D (data) regs can be used for computations, and that includes
operations such as additions an
