Thanks for everybodys help. I've gotten things working so I thought
I'd quickly write it up.
The architecture I'm working on is deliberatly simple. It has:
* An accumulator
* Fourteen general purpose registers R10 to R1E
* X and Y cache registers each backed by non-coherent (!) caches
* A st
Michael Hope wrote:
(define_expand "reload_outsi"
[(parallel [(match_operand 0 "memory_operand" "=m")
Perhaps the problem is that the output operand is an unallocated
pseudo-reg instead of a MEM. Looking at other targets that have
reload_out* patterns, I see that they have predicates that
Thanks Jim and Ian. I've added a secondary_reload which does this:
...
if (code == MEM)
{
if (fp_plus_const_operand(XEXP(x, 0), mode))
{
sri->icode = in_p ? CODE_FOR_reload_insi : CODE_FOR_reload_outsi;
return NO_REGS;
}
where fp_plus_const_operand
Michael Hope wrote:
HI there. I'm working on porting gcc to a new architecture which only
does indirect addressing - there is no indirect with displacement.
The IA-64 target also has only indirect addressing. Well, it has some
auto-increment addressing modes too, but that isn't relevant here
Michael Hope writes:
> HI there. I'm working on porting gcc to a new architecture which only
> does indirect addressing - there is no indirect with displacement.
>
> The problem is with spill locations in GCC 4.4.0. The elimination
> code correctly elimates the frame and args pointer and replac
