Ye, Joey wrote:
Vladimir Makarov [mailto:vmaka...@redhat.com] wrote:
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
semantics defi
Maxim Kuvyrkov [mailto:ma...@codesourcery.com] wrote:
> Yes, it does depend on this assumption and the comment states exactly that.
What I concerned is that the assumption may be broken someday, unless scheduler
guarantees it.
> Which check[s] do you have in mind, the gcc_assert's? Also, out of
Ye, Joey wrote:
Maxim and Vladimir Wrote:
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplified
Vladimir Makarov [mailto:vmaka...@redhat.com] wrote:
> It was supposed to have two latency definitions at most (one in
> define_insn_reservation and another one in define_bypass). That time it
> seemed enough for all processors supported by GCC. It also simplified
> semantics definition when t
Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>
>> It was supposed to have two latency definitions at most (one in
>> define_insn_reservation and another one in define_bypass). That time it
>> seemed enough for all processors supported by GCC. It also simplified
>>
Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>
>> It was supposed to have two latency definitions at most (one in
>> define_insn_reservation and another one in define_bypass). That time it
>> seemed enough for all processors supported by GCC. It also simplified
>>
Vladimir Makarov wrote:
Ye, Joey wrote:
...
Anyone can help me through this please?
It was supposed to have two latency definitions at most (one in
define_insn_reservation and another one in define_bypass). That time it
seemed enough for all processors supported by GCC. It also simplif
Ye, Joey wrote:
When I write schedule model for following instructions:
Insn1: mov %r1, %r2
Insn2: mov %r1, %r3
Insn3: foo %r2, %r3 (foo is a 3 op insn, for example, %r3 = %r3 << %r2)
Latency from insn1 to insn3 is x cycles, and latency from insn2 to insn3 is y
cycles. x != y.
Both insn1 and
