yazdanbakhsh writes:
> I'm working with GCC 2.7.
I think I see your problem.
> I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
>
> int
> new_arith_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> if (GE
Actually, I'm working with simplescalar and it only supports gcc 2.9.
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On 15 June 2010 14:01, yazdanbakhsh wrote:
>
> I'm working with GCC 2.7. I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
[...]
> I appreciate any help.
I think the best advice I can give you is: Use a recent GCC version.
GCC 2.7
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Hello,
> I want to limit the size of immediate field of some operation.
I think you can look at SIGNED_INT_FITS_N_BITS definition at
config/crx/crx.c
for such example.
You can write a predicate like the following; and use it when describing
the immediate
operand in the md file.
(define_predicate
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yazdanbakhsh writes:
> I did what you said, and the same error happened :(
I'm sorry you're having trouble, but if you want us to be able to help
you you need to show us precisely what you did, precisely what
happened, and what you expected to happen.
Ian
I did what you said, and the same error happened :(
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yazdanbakhsh writes:
> I want to exclude all immediate or instruction. I did this by the following
> define_insn
>
> /--
> (define_insn "iorsi3"
> [(set (match_operand:SI 0 "register_operand" "=d,d")
> (ior:SI (m
Internal compiler error: program cc1 got fatal signal 6
make: *** [libgcc2.a] Error 1
//--------------
I appreciate any help.
Bestr
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yazdanbakhsh writes:
> I want to exclude XORI from the instruction set of a cpu. I deleted all the
> XORI in md file. But when I compiled my program some XORI operation still
> exist. how this would be possible?
It could be printed directly from a .c file in your config/CPU
directory.
Ian
Hi,
I want to exclude XORI from the instruction set of a cpu. I deleted all the
XORI in md file. But when I compiled my program some XORI operation still
exist. how this would be possible?
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yazdanbakhsh writes:
> (define_insn "*bltdf"
> [(set (pc)
> (if_then_else (lt:SI (match_operand:DF 1 "" "")
>(match_operand:DF 2 "" ""))
> (match_operand 3 "pc_or_label_operand" "")
> (match_operand 4 "pc_or_label_operand" "")))]
> ""
>
> "*
> {
ng line to the mips-opc.c:
{"blt", "s,t,p",0x000d, 0x0000, 0 },
but during cmpilation, I encounter the following error:
...
_ashrdi3
_ffsdi2
_udiv_w_sdiv
_udivmoddi4
_cmpdi2
_ucmpdi2
_floatdidf
_floatdisf
_fixunsdfsi
_fixunssfsi
_fixunsdfdi
/tmp/ccrWquNC.s: Assembler messages:
/tmp/ccrWquNC.s:169: Error: illegal operands `blt'
/tmp/ccrWquNC.s:231: Error: illegal operands `blt'
make: *** [libgcc2.a] Error 1
I appreciate any help...
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yazdanbakhsh writes:
> (define_expand "cbranchsi4"
> [(set (pc)
> (if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
> (match_operand:SI 1 "register_operand" "=d,d"))
> (label_ref (match_operand 2 "" ""))
> (pc)))]
> ""
> "
s to reject an immediate operand.
>>>>>
>>>>> E.g., in mips.md this is:
>>>>>
>>>>> (define_insn "*3"
>>>>> [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>> (any_shift:GP
e insn which generates sll. Change the operand constraints and
>>>> predicates to reject an immediate operand.
>>>>
>>>> E.g., in mips.md this is:
>>>>
>>>> (define_insn "*3"
>>>> [(set (match_operand:GPR 0 "register_operand" &qu
t;>>> (define_insn "*3"
>>>> [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>> (match_operand:SI 2 "arith_operand" &q
>>> if (CONST_INT_P (operands[2]))
>>> operands[2] = GEN_INT (INTVAL (operands[2])
>>>& (GET_MODE_BITSIZE (mode) - 1));
>>>
>>> return "\t%0,%1,%2";
>>> }
>>> [(set_attr "type" "shift")
>>>(set_attr "mode" "")])
>>>
>>>
>>> For operand 2, change the predicate to register_operand and remove the
>>> 'I' constraint.
>>>
>>> Ian
>>>
>>>
>>
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>
>
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if (CONST_INT_P (operands[2]))
>> operands[2] = GEN_INT (INTVAL (operands[2])
>> & (GET_MODE_BITSIZE (mode) - 1));
>>
>> return "\t%0,%1,%2";
>> }
>> [(set_attr "type" "shift")
>>(set_attr "mode" "")])
>>
>>
>> For operand 2, change the predicate to register_operand and remove the
>> 'I' constraint.
>>
>> Ian
>>
>>
>
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> {
> if (CONST_INT_P (operands[2]))
> operands[2] = GEN_INT (INTVAL (operands[2])
> & (GET_MODE_BITSIZE (mode) - 1));
>
> return "\t%0,%1,%2";
> }
> [(set_attr "type" "shift")
>(set_attr "mode" &
yazdanbakhsh writes:
> This is the newer version. It works correctly. I just want know is there any
> other way.
Did you read what I wrote earlier?
http://gcc.gnu.org/ml/gcc/2010-05/msg00048.html
Ian
slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but they are used in other instruction
> definitions.
> It is also exist for addi/addui. Where I can find the definitions of the
t;>>> instructions? I want to force gcc to just use register shift and
>>>> register
>>>> add.
>>>
>>> There is no ss.md file in the standard gcc distribution. If
>>> SimpleScalar has a gcc port, I don't know anything about it. So it's
>>> hard to answer to your question precisely.
>>>
>>> Instructions can come from either a .md file or a .c file in the
>>> config/CPU directory used for your CPU. If those instructions are
>>> appearing in the generated assembler, then they must be in there
>>> somewhere.
>>>
>>> Ian
>>>
>>>
>>
>>
>
>
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gt;> There is no ss.md file in the standard gcc distribution. If
>> SimpleScalar has a gcc port, I don't know anything about it. So it's
>> hard to answer to your question precisely.
>>
>> Instructions can come from either a .md file or a .c file in the
>> c
yazdanbakhsh writes:
> Please assume I'm working with the MIPS. There is a little difference
> between the MIPS and what I'm actually working on it. How can I remove
> immediate logical shift right/left from the compiler?
> I mean If I want the programmer writes an immediate shift, It is compiled
; hard to answer to your question precisely.
>
> Instructions can come from either a .md file or a .c file in the
> config/CPU directory used for your CPU. If those instructions are
> appearing in the generated assembler, then they must be in there
> somewhere.
>
> Ian
>
yazdanbakhsh writes:
> I'm working on my a gcc compiler for my own written processor with the help
> of SimpleScalar.
> I want to remove "srav/slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but
but they are used in other instruction
definitions.
It is also exist for addi/addui. Where I can find the definitions of these
instructions? I want to force gcc to just use register shift and register
add.
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Ian Lance Taylor writes:
> This kind of error generally means that the operand predicate accepts
> an operand which no constraint matches. If the predicate (e.g.,
> register_operand) accepts an operand, then there must be a constraint
> that matches it. Otherwise you will get an error in
> const
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
> Thank you very much Ian and Shreyas for your quick response. So I guess,
> my question now would be, what would be an exmple that matches this
> constraint below?
>
> ((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
> (co
Thank you very much Ian and Shreyas for your quick response. So I guess,
my question now would be, what would be an exmple that matches this
constraint below?
((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (r
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
No need to send to both gcc@gcc.gnu.org and [EMAIL PROTECTED] I
removed gcc-help in this reply. Thanks.
>I am currently developing a GCC port for my own generic 32 bit
> processor. I have this following error when I tried to compile a
> benchmark
Hi all,
I am currently developing a GCC port for my own generic 32 bit
processor. I have this following error when I tried to compile a
benchmark.
(insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (reg:SI 12 r1
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