On Thu, 27 Nov 2014, Mathias Roslund wrote:
> But isn't the result of an 8bit signed divide the same as the result of
> a 32bit signed divide when both operands are in the 8bit range? That is,
> shouldn't the optimizers be able to do the same for signed divide as
> well as shift operations?
At
> From: Joern Rennecke [mailto:joern.renne...@embecosm.com]
> Sent: Wednesday, November 26, 2014 6:13 PM
> To: Mathias Roslund
> Cc: GCC
> Subject: Re: Machine description and code generation
>
> On 26 November 2014 at 16:48, Mathias Roslund
> wrote:
> > Since the
On 26 November 2014 at 16:48, Mathias Roslund wrote:
> Since then I've added more instructions and gotten to the point where most
> stuff seems to be working. My current issue is that signed divide and all
> shift operations insists on sign/zero extending the operands, resulting in
> 32bit operati
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Jeff Law
> Sent: Wednesday, October 29, 2014 9:36 PM
> To: Mathias Roslund; gcc@gcc.gnu.org
> Subject: Re: Machine description and code generation
>
> On 10/29/14 07:40, Mathias Roslund wrote:
&
On 10/29/14 07:40, Mathias Roslund wrote:
Hello,
I'm considering attempting a 65816 target but decided it would be a good
idea to start with something simple in order to learn how GCC generate
code. So I created a minimal machine description with just two
instructions (plus the mandatory nop/jum
Hello,
I'm considering attempting a 65816 target but decided it would be a good
idea to start with something simple in order to learn how GCC generate
code. So I created a minimal machine description with just two
instructions (plus the mandatory nop/jump/etc):
(define_mode_iterator INT [QI HI SI
