Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-06-04 Thread Klaus Pedersen
On Mon, Jun 4, 2012 at 1:44 AM, Richard Sandiford wrote: > Klaus Pedersen writes: [...] >> My original fix, that use sane cost for the ACC_REGS: gpr_acc_cost_3.patch > > Why sane?  Transfers from and (especially) to HI and LO really are > expensive on many processors.  Obviously it'd be nice at s

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-06-03 Thread Richard Sandiford
Klaus Pedersen writes: > On Tue, May 29, 2012 at 6:55 AM, Vladimir Makarov wrote: >> On 05/28/2012 03:09 PM, Richard Sandiford wrote: >>> >>> Klaus Pedersen  writes: The summery goes something like this: It is possible for the second pass of ira to get confused and decide that

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-06-03 Thread Klaus Pedersen
On Tue, May 29, 2012 at 6:55 AM, Vladimir Makarov wrote: > On 05/28/2012 03:09 PM, Richard Sandiford wrote: >> >> Klaus Pedersen  writes: >>> >>> The summery goes something like this: >>> >>> It is possible for the second pass of ira to get confused and decide that >>> NO_REGS or a hard float regi

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-30 Thread Vladimir Makarov
On 05/30/2012 10:27 PM, Klaus Pedersen wrote: Thanks for the pointer, On Wed, May 30, 2012 at 2:40 AM, Vladimir Makarov wrote: Here is an extract from my article from GCC Summit 2004 proceedings. It is interesting to note that the pass also implicitly does code selection. Regclass works in

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-30 Thread Klaus Pedersen
Thanks for the pointer, On Wed, May 30, 2012 at 2:40 AM, Vladimir Makarov wrote: > Here is an extract from my article from GCC Summit 2004 proceedings. > > It is interesting to note that the pass also implicitly does code > selection. Regclass works in two passes. On the first pass, it > defin

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-29 Thread Vladimir Makarov
On 05/29/2012 02:33 AM, Richard Sandiford wrote: Hi Vlad, Thanks for the answer. Vladimir Makarov writes: On 05/28/2012 03:09 PM, Richard Sandiford wrote: Or is it a conceptual part of the algorithm? No. More generally, what kind of situations does the second pass help with? I can

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Richard Sandiford
Hi Vlad, Thanks for the answer. Vladimir Makarov writes: > On 05/28/2012 03:09 PM, Richard Sandiford wrote: >>Or is it a conceptual part of the algorithm? > No. >>More generally, >> what kind of situations does the second pass help with? > I can not show such situations right now but I d

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Vladimir Makarov
On 05/28/2012 03:09 PM, Richard Sandiford wrote: Klaus Pedersen writes: The summery goes something like this: It is possible for the second pass of ira to get confused and decide that NO_REGS or a hard float register are better choices for the result of the 2 operand mult. First pass already o

Re: MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-05-28 Thread Richard Sandiford
Klaus Pedersen writes: > The summery goes something like this: > > It is possible for the second pass of ira to get confused and decide that > NO_REGS or a hard float register are better choices for the result of the > 2 operand mult. First pass already optimally allocated in GR_AND_MD1_REGS. Yea

MIPS: 2'nd pass of ira, causes weird register allocation for 2-op mult

2012-04-23 Thread Klaus Pedersen
The summery goes something like this: It is possible for the second pass of ira to get confused and decide that NO_REGS or a hard float register are better choices for the result of the 2 operand mult. First pass already optimally allocated in GR_AND_MD1_REGS. Two pass ira is enabled with "-fexpe