Re: How to support 40bit GP register - Take two

2009-12-18 Thread Hans-Peter Nilsson
Sorry if I misunderstood, but... On Fri, 18 Dec 2009, Mohamed Shafi wrote: > 2009/12/18 Hans-Peter Nilsson : > > On Fri, 20 Nov 2009, Mohamed Shafi wrote: > >> I tried implementing the suggestion given by Richard, but got into > >> issues. The GCC frame work is written assuming that there are no

Re: How to support 40bit GP register - Take two

2009-12-17 Thread Mohamed Shafi
2009/12/18 Hans-Peter Nilsson : > On Fri, 20 Nov 2009, Mohamed Shafi wrote: >> I tried implementing the suggestion given by Richard, but got into >> issues. The GCC frame work is written assuming that there are no modes >> with HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * >> HOST_BITS_PER

Re: How to support 40bit GP register - Take two

2009-12-17 Thread Hans-Peter Nilsson
On Fri, 20 Nov 2009, Mohamed Shafi wrote: > I tried implementing the suggestion given by Richard, but got into > issues. The GCC frame work is written assuming that there are no modes > with HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * > HOST_BITS_PER_WIDE_INT. (Not seeing a reply regard

How to support 40bit GP register - Take two

2009-11-19 Thread Mohamed Shafi
Hello all, I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data registers and 32bit address register. Both can be used as general purpose registers. All load and store operations are 32bit. If 40bit data register is involved in load/sore the register gets sign extended. Whenever th

Re: How to support 40bit GP register

2009-11-09 Thread Richard Henderson
On 11/09/2009 06:13 AM, Mohamed Shafi wrote: Ok i have comparison patterns written in RImode. When you say that i will wind up with a selection of patterns do you mean to say that i should have patterns for operations that operate on full 40bits in RImode and disable the corresponding SImode p

Re: How to support 40bit GP register

2009-11-09 Thread Mohamed Shafi
2009/10/22 Richard Henderson : > On 10/21/2009 07:25 AM, Mohamed Shafi wrote: >> >> For accessing a->b GCC generates the following code: >> >>        move.l  (sp-16), d3 >>        lsrr.l  #<16, d3 >>        move.l  (sp-12),d2 >>        asll    #<16,d2 >>        or      d3,d2 >>        cmpeq.w #<2,d

Re: How to support 40bit GP register

2009-11-04 Thread Richard Henderson
On 11/04/2009 05:34 AM, Mohamed Shafi wrote: Load-store uses 32bits. Sign extension happens automatically. So i have choosen INT_MODE (RI, 5) and copied movsi and renamed it to movri. I have also specified that RImode need only one register. This isn't going to work. In order to get correct co

Re: How to support 40bit GP register

2009-11-04 Thread Dave Korn
Mohamed Shafi wrote: > Load-store uses 32bits. Sign extension happens automatically. So i > have choosen INT_MODE (RI, 5) and copied movsi and renamed it to > movri. I have also specified that RImode need only one register. > I get the following ICE > > internal compiler error: in immed_double_c

Re: How to support 40bit GP register

2009-11-04 Thread Mohamed Shafi
2009/10/22 Richard Henderson : > On 10/21/2009 07:25 AM, Mohamed Shafi wrote: >> >> For accessing a->b GCC generates the following code: >> >>        move.l  (sp-16), d3 >>        lsrr.l  #<16, d3 >>        move.l  (sp-12),d2 >>        asll    #<16,d2 >>        or      d3,d2 >>        cmpeq.w #<2,d

Re: How to support 40bit GP register

2009-10-21 Thread Richard Henderson
On 10/21/2009 07:25 AM, Mohamed Shafi wrote: For accessing a->b GCC generates the following code: move.l (sp-16), d3 lsrr.l #<16, d3 move.l (sp-12),d2 asll#<16,d2 or d3,d2 cmpeq.w #<2,d2 jf _L2 Because data registers are 4

How to support 40bit GP register

2009-10-21 Thread Mohamed Shafi
HI all, I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data registers and 32bit address registers that can be used as general purpose registers. When 40bit registers are used for arithmetic operations or comparison operations GCC generates code assuming that its a 32bit register.