On Wed, Dec 26, 2007 at 06:59:39AM -0800, Qing Wei wrote:
> I tried by referring the ia64.md, unfortunately it does not work. The
> insn I wrote for FMAC is as follows,
>
> (define_insn "maddsi4"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (plus:SI (mult:SI (match_operand:SI 1 "register
I tried by referring the ia64.md, unfortunately it does not work. The
insn I wrote for FMAC is as follows,
(define_insn "maddsi4"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))
(match_ope
> Could someone give some hints of how to describe a FMAC (float mult and
> add) insn in machine description, it matches d = b*c+a, which is a four
> operands float instrution. With a glimp through the array optabs[] in
> genopinit.c, it seems no OP handler could match FMAC operation?
Correct. I
Qing Wei wrote:
> Could someone give some hints of how to describe a FMAC (float mult and
> add) insn in machine description, it matches d = b*c+a, which is a four
> operands float instrution.
There are plenty of examples in ia64.md and rs6000.md.
Hi,
Could someone give some hints of how to describe a FMAC (float mult and
add) insn in machine description, it matches d = b*c+a, which is a four
operands float instrution. With a glimp through the array optabs[] in
genopinit.c, it seems no OP handler could match FMAC operation? And I
found a fun
