Re: Expanding a load instruction

2009-06-11 Thread Jean Christophe Beyler
Thanks, I've pretty much finished this part of the implementation and it seems to be working well. Thank you all very much for your help, Jc On Wed, Jun 10, 2009 at 11:12 AM, Dave Korn wrote: > Jean Christophe Beyler wrote: > >> It seems that I should do the same as them no for my solution. First

Re: Expanding a load instruction

2009-06-10 Thread Dave Korn
Jean Christophe Beyler wrote: > It seems that I should do the same as them no for my solution. First > implement the legitimate_address function and then probably define it > in both macros. Sounds about right. > As for the target hook, we are using GCC 4.3.2 for the moment and, > sadly, have

Re: Expanding a load instruction

2009-06-10 Thread Jean Christophe Beyler
Ok, I wrongly read what this macro did. Sorry about that. I was looking at the i386 port and use of this variable and this code came up: #ifdef REG_OK_STRICT #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ do {\ if (legitimate_address_p ((MODE),

Re: Expanding a load instruction

2009-06-10 Thread Dave Korn
Jean Christophe Beyler wrote: > I'll be looking into this but I thought that GO_IF_LEGITIMATE_ADDRESS > is for branches ? No, absolutely not. GILA is a general filter that has overall control over which forms of addressing modes used to address memory may be generated in RTL. http://gcc.gnu.or

Re: Expanding a load instruction

2009-06-10 Thread Jean Christophe Beyler
I'll be looking into this but I thought that GO_IF_LEGITIMATE_ADDRESS is for branches ? This is not my case. I've simplified my test case into: struct test { const char *name; /* full name */ chara; /* symbol */ signed char b; unsigned short c;

Re: Expanding a load instruction

2009-06-09 Thread Dave Korn
Jean Christophe Beyler wrote: > Dear all, > > I've moved forward on this issue. Again, the problem is not that the > data is not aligned but that the compiler tries to generate this > instruction: > > (set (reg:HI 141) (mem/s/j:HI (plus:DI (reg:DI 134 [ ivtmp.23 ]) > (const_int 1 [0x1]))

Re: Expanding a load instruction

2009-06-09 Thread Jean Christophe Beyler
Dear all, I've moved forward on this issue. Again, the problem is not that the data is not aligned but that the compiler tries to generate this instruction: (set (reg:HI 141) (mem/s/j:HI (plus:DI (reg:DI 134 [ ivtmp.23 ]) (const_int 1 [0x1])) [0 .geno+0 S2 A16])) And, in my target archi

Re: Expanding a load instruction

2009-06-05 Thread Dave Korn
fearyourself wrote: > In the instruction set of my architecture, the offsets of a half-load > (HImode) have to be multiples of 2. However, if I set up a structure > in a certain way, the compiler will generate: > > (mem/s/j:HI (plus:DI (reg:DI 134 [ ivtmp.23 ]) > (const_int 1 [0x1])) [0 .

Expanding a load instruction

2009-06-05 Thread fearyourself
Dear all, In the instruction set of my architecture, the offsets of a half-load (HImode) have to be multiples of 2. However, if I set up a structure in a certain way, the compiler will generate: (mem/s/j:HI (plus:DI (reg:DI 134 [ ivtmp.23 ]) (const_int 1 [0x1])) [0 .geno+0 S2 A16]) As th