Thanks Jim,
It took me a while to get back to this problem but as you
suggested, exposing only the three address instructions prior to
reload... in conjunction with implementing
TARGET_CLASS_LIKELY_SPILLED_P
has produced good results. After taking these measures I didn't
have to disparage a
On 07/30/2015 09:54 PM, Paul Shortis wrote:
> Resulting in ...
> error: unable to find a register to spill in class ‘GP_REGS’
>
> enabling lra and inspecting the rtl dump indicates that both
> alternatives (R and r) seem to be equally appealing to the allocater so
> it chooses 'R' and fails.
The
I'm working with a CPU having a restricted set of registers that can do
three address maths wheres ALL registers can do two address maths.
If I define
(define_insn "addsi3"
[ (set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (match_operand:SI 1 "register_o
