> Can any one get me the information/implementation of below mentioned
> functions?
>
> 1. operands[0] = gen_rtx_REG (SImode,REGNO (set_dest));
> 2. operands[0] = gen_highpart (SImode, set_dest);
Sure, emit-rtl.c, lines 488 and 1165.
Ben
Hi all,
Can any one get me the information/implementation of below mentioned
functions?
1. operands[0] = gen_rtx_REG (SImode,REGNO (set_dest));
2. operands[0] = gen_highpart (SImode, set_dest);
Are both functionalities similiar if i use the above functions to get
the 32 bit word from a 64 bit
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> (insn 106 36 107 6 (set (reg:SI 13 a5)
> (const_int -20 [0xffec])) 17 {movsi_short_const} (nil)
> (nil))
>
> (insn 107 106 108 6 (parallel [
> (set (reg:SI 13 a5)
> (plus:SI (reg:SI 13 a5)
>
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> 1. Does attribute length affect the calculation of offset?
It does if you tell it to. The "length" attribute must be managed
entirely by your backend. Most backends with variable size branches
use the length attribute to select which branch insn to
Hi all,
Finally got the combined compare_and_branch instruction to work. But
it has some side effects while testing other files.
20010129-1.s: Assembler messages:
20010129-1.s:46: Error: Value of 0x88 too large for 7-bit relative
instruction offset
I just designed my compare and branch insn as
Hello all,
While going through the RTL dumps, I noticed a few things which i need
to get clarified.
Below is the extract, in which i get the doubt.
(insn 106 36 107 6 (set (reg:SI 13 a5)
(const_int -20 [0xffec])) 17 {movsi_short_const} (nil)
(nil))
(insn 107 106 108 6 (parallel [
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> I have used cbranchmode4 instruction to generate combined compare and
> branch instruction.
>
> (define_insn "cbranchmode4"
> (set (pc) (if_then_else
> (match_operator:CC 0 "comparison_operator"
> [ (match_operand:SI 1
Hi all,
I have used cbranchmode4 instruction to generate combined compare and
branch instruction.
(define_insn "cbranchmode4"
(set (pc) (if_then_else
(match_operator:CC 0 "comparison_operator"
[ (match_operand:SI 1 "register_operand" "r,r")
(match_o
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> I am trying to combine the compare and branch instruction. But my
> instructions are not getting generated as my operands are not matched
> properly.
>
> Previously for individual compare instructions, i had
> operand 0 - Register operand
> operand 1
Hi all,
I am trying to combine the compare and branch instruction. But my
instructions are not getting generated as my operands are not matched
properly.
Previously for individual compare instructions, i had
operand 0 - Register operand
operand 1 - Non memory operand.
For branch instruction,
op
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> The relevant part of RTL dump of fgcse pass is given below:
>
> (insn 13 12 50 0 (set (reg:CC 21 cc)
> (compare:CC (reg:SI 29 [ n ])
> (const_int 30 [0x1e]))) 68 {*cmpsi_internal} (nil)
> (nil))
>
> (insn 50 13 53 0 (paralle
Hi All,
GCC 4.1.1
This small bit of code from one of the test suites (
gcc.c-torture/execute/20020611-1.c)worked fine with all optimization
except size optimization -Os.
unsigned int p;
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> The problem due to which the below mentioned program was not working
> is because of CODE HOISTING pass. I just masked the code hoisting step
> and the program worked fine.
At this point, if you want us to be able to give you useful
suggestions, you
Hi all,
The problem due to which the below mentioned program was not working
is because of CODE HOISTING pass. I just masked the code hoisting step
and the program worked fine.
1. The instruction no's 11, 12, 13 are removed when -Os optimization
is enabled (it considers n, h as dead). Is there a
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> > > This small bit of code worked fine with all optimization except Os.
> > >
> > > unsigned int n = 30;
> > > void x ()
> > > {
> > > unsigned int h;
> > > h = n <= 30; // Line 1
> > > if (h)
> > >p = 1;
> > > else
> > >p = 0;
>
> since p is a global variable, it can be used in other functions. Any
> other causes?
The first thing to do is to post a reproducer. As Ian said, your code doesn't
even compile...
--
Eric Botcazou
Rohit Arul Raj wrote:
I am working with a GCC Cross compiler version 4.1.1.
This small bit of code worked fine with all optimization except Os.
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
}
[...]
3. What are the probabl
On 26 Oct 2006 22:02:04 -0700, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> This small bit of code worked fine with all optimization except Os.
>
> unsigned int n = 30;
> void x ()
> {
> unsigned int h;
> h = n <= 30; // Line 1
> if (h)
"Rohit Arul Raj" <[EMAIL PROTECTED]> writes:
> This small bit of code worked fine with all optimization except Os.
>
> unsigned int n = 30;
> void x ()
> {
> unsigned int h;
> h = n <= 30; // Line 1
> if (h)
>p = 1;
> else
>p = 0;
> }
>
> when we tried to debug the emitted
Hi all,
I am working with a GCC Cross compiler version 4.1.1.
This small bit of code worked fine with all optimization except Os.
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
}
when we tried to debug the emitted RTL instruction
On Mon, 2006-10-23 at 16:14 +0530, Rohit Arul Raj wrote:
> Hi all,
>
> This small bit of code worked fine with all optimization except Os.
If you are working with 4.0 and greater, there are optimizations that
happen before RTL, called the Tree-ssa optimizations. The optimization
you are noticing
Hi all,
This small bit of code worked fine with all optimization except Os.
unsigned int n = 30;
void x ()
{
unsigned int h;
h = n <= 30; // Line 1
if (h)
p = 1;
else
p = 0;
}
when we tried to debug the emitted RTL instruction for Os, it was
found that RTL instruction for Li
> a) To which register is the value of n copied? if a5 is the register
> what is 13 and [28]
All of those numbers refer to the same register -
13 is the number of the register; a5 is the name of the register
(if it is an hard register);
[28] is the number of the old pseudo register.
(please look
Hi all,
I need some clarification in understanding the below mentioned RTL Expressions
1. (insn 11 10 12 0
gcc/testsuite/gcc.c-torture/execute/20020611-1.c:13 (parallel [
(set (reg/f:SI 13 a5 [28])
(symbol_ref:SI ("n") [flags 0x2] ))
(clobber (reg:CC 21 cc))
On Tue, Oct 17, 2006 at 01:10:02AM -0700, Mohamed Shafi wrote:
> > It is because matching has not yet been attempted.
>
> ok.. so what is the option to get hold of a rtl dump after all the matching
> is done
-fdump-rtl-vregs, although if you want to see the prologue and epilogue
code too, -fd
; Revital1 Eres <[EMAIL PROTECTED]>
Sent: Tuesday, October 17, 2006 1:21:30 PM
Subject: Re: Abt RTL expression
On Mon, Oct 16, 2006 at 09:32:58PM -0700, Mohamed Shafi wrote:
>
> In th document
> http://gcc.gnu.org/onlinedocs/gccint/Insns.html#Insns
>
> it is said that "
On Mon, Oct 16, 2006 at 09:32:58PM -0700, Mohamed Shafi wrote:
>
> In th document
> http://gcc.gnu.org/onlinedocs/gccint/Insns.html#Insns
>
> it is said that "An integer that says which pattern in the machine
> description matches
> this insn, or -1 if the matching has not yet been attempted.Su
cc.gnu.org
Sent: Monday, October 16, 2006 7:28:42 PM
Subject: Re: Abt RTL expression
On Mon, Oct 16, 2006 at 05:20:44AM -0700, Mohamed Shafi wrote:
> hello all,
>
> Sorry i am asking this kind of question.This might be weird to most of you
> but i am new to GCC.
> Can somebody te
On Mon, Oct 16, 2006 at 05:20:44AM -0700, Mohamed Shafi wrote:
> hello all,
>
> Sorry i am asking this kind of question.This might be weird to most of you
> but i am new to GCC.
> Can somebody tell me how to analyze the below instruction pattern
>
> (insn 8 6 9 1 (parallel [
> (set (
(insn 8 6 9 1 (parallel [
(set (reg/f:SI 32)
(symbol_ref:SI ("t") ))
(clobber (reg:CC 21 cc))
]) -1 (nil)
(nil))
Here is an answer to your first question:
8 6 9 are the serial numbers of the current, previous and next instructions
in the instru
hello all,
Sorry i am asking this kind of question.This might be weird to most of you but
i am new to GCC.
Can somebody tell me how to analyze the below instruction pattern
(insn 8 6 9 1 (parallel [
(set (reg/f:SI 32)
(symbol_ref:SI ("t") ))
(clobber (reg:
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