On Wed, Dec 7, 2022 at 10:24 AM Sebastian Huber
wrote:
>
>
>
> On 07.12.22 10:09, Richard Biener wrote:
> > On Wed, Dec 7, 2022 at 9:51 AM Sebastian Huber
> > wrote:
> >> On 06.12.22 17:08, Richard Biener wrote:
> >>> Likely. I'd use the gimple_build () API from gimple-fold.h which
> >>> builds
On 04.11.22 09:27, Sebastian Huber wrote:
Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not support atomic profile update, single mode is
selecte
On 07.12.22 10:09, Richard Biener wrote:
On Wed, Dec 7, 2022 at 9:51 AM Sebastian Huber
wrote:
On 06.12.22 17:08, Richard Biener wrote:
Likely. I'd use the gimple_build () API from gimple-fold.h which
builds the expression(s) to a gimple_seq creating necessary temporaries
on-the-fly and t
On Wed, Dec 7, 2022 at 9:51 AM Sebastian Huber
wrote:
>
> On 06.12.22 17:08, Richard Biener wrote:
> > Likely. I'd use the gimple_build () API from gimple-fold.h which
> > builds the expression(s) to a gimple_seq creating necessary temporaries
> > on-the-fly and then insert that sequence on the e
On 06.12.22 17:08, Richard Biener wrote:
Likely. I'd use the gimple_build () API from gimple-fold.h which
builds the expression(s) to a gimple_seq creating necessary temporaries
on-the-fly and then insert that sequence on the edge.
Thanks, I will have a look at this.
I am struggling to conver
On Tue, Dec 6, 2022 at 2:11 PM Sebastian Huber
wrote:
>
> On 05/12/2022 08:44, Richard Biener wrote:
> > On Mon, Dec 5, 2022 at 8:26 AM Sebastian Huber
> > wrote:
> >> On 08/11/2022 11:25, Richard Biener wrote:
> It would be great to have a code example for the construction of the "if
> >>>
On 05/12/2022 08:44, Richard Biener wrote:
On Mon, Dec 5, 2022 at 8:26 AM Sebastian Huber
wrote:
On 08/11/2022 11:25, Richard Biener wrote:
It would be great to have a code example for the construction of the "if
(f()) f();".
I think for the function above we need to emit __atomic_fetch_add_
On Mon, Dec 5, 2022 at 8:26 AM Sebastian Huber
wrote:
>
> On 08/11/2022 11:25, Richard Biener wrote:
> >> It would be great to have a code example for the construction of the "if
> >> (f()) f();".
> > I think for the function above we need to emit __atomic_fetch_add_8,
> > not the emulated form be
On 08/11/2022 11:25, Richard Biener wrote:
It would be great to have a code example for the construction of the "if
(f()) f();".
I think for the function above we need to emit __atomic_fetch_add_8,
not the emulated form because we cannot insert the required control
flow (if (f()) f()) on an edge
On Tue, Nov 8, 2022 at 1:00 PM Sebastian Huber
wrote:
>
> On 08.11.22 11:25, Richard Biener wrote:
> >> How do I get ((unsigned int *) &val) + 1 from tree addr?
> >>
> >> It would be great to have a code example for the construction of the "if
> >> (f()) f();".
> > I think for the function above w
On 08.11.22 11:25, Richard Biener wrote:
How do I get ((unsigned int *) &val) + 1 from tree addr?
It would be great to have a code example for the construction of the "if
(f()) f();".
I think for the function above we need to emit __atomic_fetch_add_8,
not the emulated form because we cannot in
On Tue, Nov 8, 2022 at 7:22 AM Sebastian Huber
wrote:
>
> On 05.11.22 12:18, Richard Biener wrote:
> > On Fri, Nov 4, 2022 at 9:28 AM Sebastian Huber
> > wrote:
> >> Hello,
> >>
> >> even recent 32-bit architectures such as RISC-V do not support 64-bit
> >> atomic operations. Using -fprofile-up
On 05.11.22 12:18, Richard Biener wrote:
On Fri, Nov 4, 2022 at 9:28 AM Sebastian Huber
wrote:
Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not supp
On Fri, Nov 4, 2022 at 9:28 AM Sebastian Huber
wrote:
>
> Hello,
>
> even recent 32-bit architectures such as RISC-V do not support 64-bit
> atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
> RV32GC ISA yields:
>
> warning: target does not support atomic profile update, sing
On 04/11/2022 10:53, Gabriel Paubert wrote:
2. Use
if (__atomic_add_fetch_4 ((unsigned int *) &val, 1, __ATOMIC_RELAXED) ==
0)
__atomic_fetch_add_4 (((unsigned int *) &val) + 1, 1, __ATOMIC_RELAXED);
if 32-bit atomics are available.
This assumes little-endian byte order.
Yes, but thi
On Fri, Nov 04, 2022 at 09:27:34AM +0100, Sebastian Huber wrote:
> Hello,
>
> even recent 32-bit architectures such as RISC-V do not support 64-bit atomic
> operations. Using -fprofile-update=atomic for the 32-bit RISC-V RV32GC ISA
> yields:
>
> warning: target does not support atomic profile up
Hello,
even recent 32-bit architectures such as RISC-V do not support 64-bit
atomic operations. Using -fprofile-update=atomic for the 32-bit RISC-V
RV32GC ISA yields:
warning: target does not support atomic profile update, single mode is
selected
For multi-threaded applications it is quit
17 matches
Mail list logo
