Janis Johnson <[EMAIL PROTECTED]> wrote on 18/12/2006 20:25:47:
> On Mon, Dec 18, 2006 at 01:19:03PM +0200, Dorit Nuzman wrote:
> > Janis Johnson <[EMAIL PROTECTED]> wrote on 15/12/2006 03:12:44:
> > >
> > > I seem to recall from long ago that some processors support
generating,
> > > and possibly
On Mon, Dec 18, 2006 at 01:19:03PM +0200, Dorit Nuzman wrote:
> Janis Johnson <[EMAIL PROTECTED]> wrote on 15/12/2006 03:12:44:
> >
> > I seem to recall from long ago that some processors support generating,
> > and possibly running, multiple kinds of vector instructions.
>
> maybe you're thinking
Janis Johnson <[EMAIL PROTECTED]> wrote on 15/12/2006 03:12:44:
> Checks for vector instruction support are spreading throughout the
> testsuite. I'd like to pull the basic logic into a single place that
> can be referenced wherever it's needed. What's there now isn't always
> consistent and the
Checks for vector instruction support are spreading throughout the
testsuite. I'd like to pull the basic logic into a single place that
can be referenced wherever it's needed. What's there now isn't always
consistent and there might be new things we can do if the information
is presented in a con
