On 7/27/2022 12:58 AM, Richard Biener via Gcc wrote:
On Tue, Jul 26, 2022 at 8:55 PM Surya Kumari Jangala via Gcc
wrote:
Hi,
I am working on PR105586. This is a -fcompare-debug failure, with the
differences starting during sched1 pass. The sequence of two instructions in a
basic block (blo
Hi Richard,
On 27/07/22 12:28 pm, Richard Biener wrote:
> On Tue, Jul 26, 2022 at 8:55 PM Surya Kumari Jangala via Gcc
> wrote:
>> To fix the issue of insns being assigned different cycles, there are two
>> possible solutions:
>>
>> 1. Modify no_real_insns_p() to treat a DEBUG insn as a non-rea
On Tue, Jul 26, 2022 at 8:55 PM Surya Kumari Jangala via Gcc
wrote:
>
> Hi,
> I am working on PR105586. This is a -fcompare-debug failure, with the
> differences starting during sched1 pass. The sequence of two instructions in
> a basic block (block 4) is flipped with -g.
> In addition to this,
Hi,
I am working on PR105586. This is a -fcompare-debug failure, with the
differences starting during sched1 pass. The sequence of two instructions in a
basic block (block 4) is flipped with -g.
In addition to this, another difference is that an insn is assigned a different
cycle in debug vs non
