Re: [ARM]Extra load store/instructions compared to gcc-3.4

2012-04-25 Thread Alexey Kravets
Hi, On Wed, Apr 25, 2012 at 05:00:40PM +0400, Alexander Monakov wrote: > Hi, > > This is a case when ivopts pass makes too many induction variables, exceeding > the number of available registers. If you want to debug it, see > ivopts_global_cost_for_size in tree-ssa-loop-ivopts.c and its callers;

Re: [ARM]Extra load store/instructions compared to gcc-3.4

2012-04-25 Thread Alexander Monakov
Hi, This is a case when ivopts pass makes too many induction variables, exceeding the number of available registers. If you want to debug it, see ivopts_global_cost_for_size in tree-ssa-loop-ivopts.c and its callers; perhaps, the issue is that it fails to account for IVs created in inner loops wh

[ARM]Extra load store/instructions compared to gcc-3.4

2012-04-25 Thread Alexey Kravets
Hi guys, I have a test case (shell sort, see attached) compiled with different ARM compilers: GCC-4.6.3, GCC-3.4.6, and ARMCC. Both ARMCC and GCC-3.4.6 generate quite optimal assembly while GCC-4.6.3 inserts extra load/store instructions compared to the other compilers. Can the SSA representatio