On 06/03/2016 05:54 AM, Woon yung Liu wrote:
The problem is that gen_lowpart() doesn't seem to support casting to other
modes of the same size.
It certainly does. The only place you get into trouble with gen_lowpart is
with CONST_INT, which is mode-less.
But I am already doubting that I w
Woon yung Liu writes:
> On Wednesday, June 1, 2016 5:45 AM, Richard Henderson
> wrote:
> > This is almost always incorrect, and certainly before reload.
> > You need to use gen_lowpart. There are examples in the code
>
> > fragments that I sent the other week.
>
> The problem is that gen_lowpa
On 05/29/2016 12:59 AM, Woon yung Liu wrote:
Hi Richard,
I have solved the problems with the mulv8hi3 pattern; I needed to adjust the
code within mips.c to allow the double-sized vector modes and to allow vector
modes into the LO+HI accumulators.
Yes, I should have mentioned that you would n
On 05/18/2016 05:16 AM, Woon yung Liu wrote:
I didn't know that, thanks.
I've re-done the instructions and expands, mostly based off the stuff that you
shared earlier. Unfortunately, the test function wouldn't compile:
testv.c: In function 'testv8mult':
testv.c:87:1: error: unrecognizable ins
On 05/14/2016 03:21 AM, Woon yung Liu wrote:
The current constraints allow GCC to access the 64-bit LO+HI register pair
as a single 128-bit register, so I am cheating by using both the x and wr
(new constraint for LO1+HI1) constraints.
That doesn't seem right.
The x constrant is for the hi/lo
On 05/15/2016 03:43 AM, Woon yung Liu wrote:
testv.c:70:2: note: ==> examining statement: _5 = (int) _4;
You need to implement the vec_unpack* patterns.
But how can I tell what operations are required by autovectorization, that are
currently not supported?
Well, the dumps you're looking
On 05/11/2016 04:54 AM, Woon yung Liu wrote:
I saw that the EE has the PMFHL.LH instruction, which loads the HI/LO
register pairs (containing the multiplication result) into a single destination
(i.e. truncates the multiplication result in the process), with the right order
too. I suppose that i
On 05/06/2016 09:28 PM, Woon yung Liu wrote:
Regarding multiplication of vectors, is there a way to work with a
multiplication operation that results in something like this (the result is
spread across these 3 registers), without re-ordering any elements:
RD: A6xB6, A4xB4, A2xB2, A0xA0
LO: A7
On 04/29/2016 07:54 AM, Liu Woon Yung wrote:
I've done something like that, but GCC still doesn't select the pattern to use:
(define_insn "vec_cmp"
Because you've used the wrong name. The patterns are:
OPTAB_CD(vec_cmp_optab, "vec_cmp$a$b")
OPTAB_CD(vec_cmpu_optab, "vec_cmpu$a$b")
I see
On 04/03/2016 09:12 PM, Woon yung Liu wrote:
I can't figure out how to implement comparison operations (specifically,
equals and the greater than operators). The GCC documentation mentions that
the pattern for comparison (==) should be vec_cmp, but I don't understand
why it has 4 operands and wha
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