> When do you un-parallel those instructions? And, how?
I don't; I use a C function to output such an insn group.
In that C function, I basically save the global state of final, and use
functions of final.c to output constitutent insns.
The insn group output function basically looks like this:
> Has anyone faced a similar problem before? Are there targets for which
> both VLIW and DBR are enabled? Perhaps ia64?
I did something similar a few months ago.
The problem is that haifa and the delayed branch scheduling passes don't
really fit together. delayed branch scheduling happily undoes
md.texi of mainline as of now states at line 4451ff:
@cindex @[EMAIL PROTECTED] instruction pattern
@item @[EMAIL PROTECTED]
Similar to @[EMAIL PROTECTED] but for conditional addition. Conditionally
move operand 2 or (operands 2 + operand 3) into operand 0 according to the
comparison in operand 1
