Thank you very much for your detailed response!
> I suspect your machine description says that dependency between loads and
> multiply-add has zero latency, thus allowing the scheduler to place them
> into
> one instruction group. Grep for various comments about tick_check_p
> function.
> In verb
Hi,
I recently read the articles about the selective scheduling
implementation and found it quite interesting, I especially liked the
idea of how neatly software pipelining is integrated. The target I am
working on is a VLIW DSP so obviously these things are very important
for good code generation
Hi,
I am working with an architecture where the 32bit registers (rN) are
divided into high (rNh) and low (rNl) 16bit sub registers that can in
principle be individually accessed by the instructions in the IS.
However the IS is designed so that it is beneficial to to store 16bit
values in the high
Hi Adam,
Looks like you were right! My SIZE_TYPE was undefined so it defaulted
to "long unsigned int". Setting it to "unsigned int" solved my
problems.
Thank you very much!
/Markus
2009/8/13 Adam Nemet :
> Markus L writes:
>> I run into an assert in convert_memo
Hi,
I am using gcc 4.4.1 and working on a port where
#define BITS_PER_UNIT 16
#define UNITS_PER_WORD 1
#define Pmode QImode
#define LONG_TYPE_SIZE 32
(i.e. int is 16 bits QImode, long is 32 bits HImode and pointer mode is QImode)
POINTERS_EXTEND_UNSIGNED is not defined since POINTER_SIZE is equ
Hi,
I have a question about modelling of condition codes in GCC. The
target I am considering has the following characteristics:
Associated with each register is a set of CC flags that are updated
whenever that register is used as a destination of an operation that
would normally update the CC reg
