On Mon, Jun 4, 2012 at 1:44 AM, Richard Sandiford
wrote:
> Klaus Pedersen writes:
[...]
>> My original fix, that use sane cost for the ACC_REGS: gpr_acc_cost_3.patch
>
> Why sane? Transfers from and (especially) to HI and LO really are
> expensive on many processors. Obvious
On Tue, May 29, 2012 at 6:55 AM, Vladimir Makarov wrote:
> On 05/28/2012 03:09 PM, Richard Sandiford wrote:
>>
>> Klaus Pedersen writes:
>>>
>>> The summery goes something like this:
>>>
>>> It is possible for the second pass of ira to get c
Thanks for the pointer,
On Wed, May 30, 2012 at 2:40 AM, Vladimir Makarov wrote:
> Here is an extract from my article from GCC Summit 2004 proceedings.
>
> It is interesting to note that the pass also implicitly does code
> selection. Regclass works in two passes. On the first pass, it
> defin
The summery goes something like this:
It is possible for the second pass of ira to get confused and decide that
NO_REGS or a hard float register are better choices for the result of the
2 operand mult. First pass already optimally allocated in GR_AND_MD1_REGS.
Two pass ira is enabled with "-fexpe
