RE: Code Motion after Machine Dependent Reorganization??

hanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Ian Lance Taylor [mailto:i...@google.com] Sent: Tuesday, December 30,

RE: Code Motion after Machine Dependent Reorganization??

the output assembly equivalents? I am willing to add my own hook if necessary. Thanks! Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Origin

RE: Code Motion after Machine Dependent Reorganization??

h the instruction chain in the wrong way? Any help is deeply appreciated! Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

Code Motion after Machine Dependent Reorganization??

iated! Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

RE: Machine Dependent Reorganization Question

Thank you Ian for your quick response. This is what I want to do: I want the scheduling phase to say an RTX X must be allocated registers from Register CLASS A. So how can I tell register allocator to do this? Thanks, -Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for

Machine Dependent Reorganization Question

ppreciated! Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

Register Allocation Question.

, But if I want to schedule this RTL to Class2. What can I do? I see that GCC doesn't change the register number if it already holds a hard-register. Any help is highly appreciated. Please CC me in your response since I am not a subscribed member. Thanks, Balaji V. Iyer. -- Balaji V

RE: GCC Eliminates my Custom RTL ..How to stop this?

. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Andrew Haley [mailto:[EMAIL PROTECTED] Sent: Monday, October 27, 2008 6:07 AM To

GCC Eliminates my Custom RTL ..How to stop this?

hases is deleting this instruction. My question is, how can I "tell" GCC to never remove this instruction (or RTL)? This instruction doesn't take any register values or write any registers, just accepts an immediate field. Any help is greatly appreciated! Than

Inserting Custom RTLs by the Haifa Scheduler

. Now, I want this instructoin to be inserted at specific points...How can I do it? What function shiould I call to output this RTL? Any help is highly appreciated! Please CC me in the answer since I am not a subscribed member of GCC. Regards, Balaji V. Iyer. -- Balaji V. Iyer PhD

Adding NEW Specialized RTL into GCC

insert). So what are the steps necessary for me to acomplish this? Any help is greatly appreciated, Thanks, Balaji V. Iyer. PS. Please CC me in your response since I am not subscribed to this mailing list. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable

STRIP NOPS Question

since I am not a subscribed to this list. Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Candidate, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

MAX_CONSTRAINT VALUE

RGET_ASM_ALIGNED_INT_OP \ {TARGET_ASM_ALIGNED_HI_OP, \ TARGET_ASM_ALIGNED_SI_OP, \ ========== Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient

RE: Help with GCC on Cygwin

686-pc-cygwin-as... no checking for as... as checking for i686-pc-cygwin-dlltool... no checking for dlltool... dlltool checking for i686-pc-cygwin-ld... no checking for ld... ld checking for i686-pc-cygwin-nm... no checking for nm... nm checking for i686-pc-cygwin-ranlib... no checking for ranlib.

Help with GCC on Cygwin

odes.exe'. Stop. I am currently using cygwin on a x86 machine, gcc version 4.0.2 (I have to use this version...can't use a diferent one), Any help is very highly appreciated! Thanking You, Yours Sincerely, Balaji V. Iyer. PS. Here is the output I received right after I ra

Adding extra instructions in the Ready List

help is greatly appreciated! Please feel free to ask me if you need additional clarification Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University

Question about Register Class Allocation

additional clarification. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

Help with GCC RTL and Register Allocator

priate alternative, not pick the first one from the different alternatives. Any help is highly appreciated. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University.

UNIQUE ID (INSN UID) Question

identifier for program level? Any help or suggestion is highly appreciated. Thanks, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -- Balaji V

Segmented Register file Implementation

flag (or create a certain FLAG) on the instruction (I know instruction is an RTX structure) so that the register allocator can recognize this? Any help is greatly appreciated. Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable

RE: Help with another constraint

. -Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Rask Ingemann Lambertsen [mailto:[EMAIL PROTECTED] Sent: Monday, December 17

RE: Help with another constraint

I do in that case? Thanks, Baljai V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department of Electrical and Computer Engineering, North Carolina State University. -Original Message- From: Revital1 Eres [mailto:[EMAIL PROTECTED

RE: Help with another constraint

t: return \"invalid alternative\"; } " To give a quick explanation: p = register numbers between 0-31 (inclusive) q = register numbers between 32-63 (inclusive) I = constant int value: ((VALUE) >=-32768 && (VALUE) <=32767) So, what am I missing? Any hel

RE: Help with another constraint

error: in final_scan_insn, at final.c:2439 Please submit a full bug report, with preprocessed source if appropriate. See http://gcc.gnu.org/bugs.html> for instructions. make[2]: *** [libgcc/./_negdi2.o] Error 1 make[2]: Leaving directory -Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center

Help with another constraint

lt; FIRST_PSEUDO_REGISTER; regno++) \ if (regs_ever_live[regno] && ! call_used_regs[regno]) \ offset += 4; \ ADDR = plus_constant (regs, offset + (DEPTH)); } } What am I doing wrong?? ANy help is highly highly appreciated! Yours Sincerely, Balaji V. Iyer.

Help with the Machine Description

r16) with an offset of 0which I have handled already in my machine description...so what can this be? Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. -- Balaji V. Iyer PhD Student, Center for Efficient, Scalable and Reliable Computing, Department

Register Numbers during machine dependent reorg?

es of config/mips directory. Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. Please CC me in your response since I am not a subscriber of this mailing list. Balaji V. Iyer PhD Student, Center for Efficient, S

RE: Vectorizer in GCC 4.0

Thank you very much Mr. Naishlos. -Balaji V. Iyer. -Original Message- From: Dorit Naishlos [mailto:[EMAIL PROTECTED] Sent: Monday, November 21, 2005 3:47 PM To: Balaji V. Iyer Cc: gcc@gcc.gnu.org Subject: Re: Vectorizer in GCC 4.0 > Hello Everyone, > I am interested in k

Vectorizer in GCC 4.0

Hello Everyone, I am interested in knowing more about the vectorizer in GCC. Does anyone have or know of any statistics about the percentage of loops that can be vectorized in some benchmarks like MediaBench, SPEC2K and so forth? Thanking You, Yours Sincerely, Balaji V. Iyer.

Extracting destination register from an instruction

impression that the only way I can do this is in the machine_dependent reorganization phase? Is there another way to do this? Also, how can I extract destination register information from the instruction? Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS

Explicit NOPs for a VLIW Machine

(or during scheduling phase) itself (or a better way to do this)? Thanks, Balaji V. Iyer.

Re: Question about Machine Description

his correct? Thanks, Balaji V. Iyer. PS. I am sorry for posting in both the mailing list. Ian Lance Taylor wrote: > "Balaji V. Iyer" <[EMAIL PROTECTED]> writes: > > No need to send to both gcc@gcc.gnu.org and [EMAIL PROTECTED] I > removed gcc-help in this reply.

Question about Machine Description

urs Sincerely, Balaji V. Iyer. PS. Please CC me since I am not a subscribed member of this list.

Help with GCC

ht direction to go about doing this. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. CC's greatly appreciated.

DFA recognizer

enRISC_DFA") I know it is including it and compiling it with the rest of hte GCC Source code. Any help is highly appreciated. Thanking You, Yours Sincerely, Balaji V. Iyer. PS. CC's appreciated.

"insn_dependent_p" substitution for GCC 4.0

hat in the ChangeLog.12 that this function was removed. What can I use in GCC-4.0.0 that will take 2 instructions and see if there is a dependency between them? I was using this instruction in the machine dependent reorganization function. Any help is greatly valued. Thanking You, Yours Sincerely, Bala