Re: Stefan Schulze Frielinghaus appointed s390x port co-maintainer

2024-09-30 Thread Andreas Krebbel via Gcc
Great job, Stefan! Congratulations! Thank you David! Bye, Andreas On 9/30/24 16:33, David Edelsohn via Gcc wrote: I am pleased to announce that the GCC Steering Committee has appointed Stefan Schulze Frielinghaus as a s390x port co-maintainer. Please join me in congratulating Stefan on his n

[Committed] IBM Z: Fix ICE in expand_perm_as_replicate

2024-06-10 Thread Andreas Krebbel via Gcc
The current implementation assumes to always be invoked with register operands. For memory operands we even have an instruction though (vlrep). With the patch we try this first and only if it fails force the input into a register and continue. vec_splats generation fails for single element 128bit

Re: CFI for saved argument registers

2022-05-31 Thread Andreas Krebbel via Gcc
On 5/16/22 08:29, Andreas Krebbel via Gcc wrote: > Hi, > > I'm trying to provide a simple dwarf unwinder with access to the > argument register content. The goal is to make this information > available for optimized code without having to access debug > information for thi

Re: CFI for saved argument registers

2022-05-16 Thread Andreas Krebbel via Gcc
On 5/16/22 16:39, Andreas Schwab wrote: > On Mai 16 2022, Andreas Krebbel via Gcc wrote: > >> The only way I see right now is adding a new reg note to invalidate >> the save information in the reg_save array in dwarf2cfi. >> >> Would this be acceptable? Is there pe

CFI for saved argument registers

2022-05-15 Thread Andreas Krebbel via Gcc
Hi, I'm trying to provide a simple dwarf unwinder with access to the argument register content. The goal is to make this information available for optimized code without having to access debug information for things like call site args. The extra overhead of saving the values to the stack is accep

Re: GCC 11.2.1 Status Report (2022-04-13), branch frozen for release

2022-04-14 Thread Andreas Krebbel via Gcc
On 4/13/22 09:30, Richard Biener via Gcc wrote: > > Status > == > > The gcc-11 branch is now frozen in preparation for a GCC 11.3 release > candidate and the GCC 11.3 release next week. All changes now require > release manager approval. Hi, I would like to push: https://gcc.gnu.org/piper

Re: Urgent GCC ABI backend maintainer ping re zero width bitfield passing (PR102024)

2022-03-21 Thread Andreas Krebbel via Gcc
On 3/21/22 17:28, Jakub Jelinek wrote: > Hi! > > I'd like to ping port maintainers about > https://gcc.gnu.org/PR102024 > > As I wrote, the int : 0 bitfields are present early in the TYPE_FIELDS > during structure layout and intentionally affect the layout. > We had some code to remove those from

Re: RFC: New mechanism for hard reg operands to inline asm

2021-06-04 Thread Andreas Krebbel via Gcc
On 6/4/21 8:18 PM, Paul Koning wrote: ... > Yes, I would think this should be made a general mechanism that any target > could use. > > I wonder if instead of creating a new mechanism you could do this simply by > creating new constraint names, where each name matches exactly one hard > registe

RFC: New mechanism for hard reg operands to inline asm

2021-06-04 Thread Andreas Krebbel via Gcc
Hi, I wonder if we could replace the register asm construct for inline assemblies with something a bit nicer and more obvious. E.g. turning this (real world example from IBM Z kernel code): int diag8_response(int cmdlen, char *response, int *rlen) { register unsigned long reg2 asm ("2") =