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Hi,
I've seen some bogus warning in GCC that suggests that some use of auto
may cause undefined behavior (due to double evaluation).
$ cat auto.c
#include
int
main(void)
{
int i = 3;
int a[2 * i];
int (*p)[2 * i];
i = 1;
p = &a;
auto q = p +
Snapshot gcc-12-20240808 is now available on
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and on various mirrors, see https://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 12 git branch
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On 8/8/24 10:26 AM, Stefan Schulze Frielinghaus wrote:
Since you installed this idea into my brain, I gave it a try. Maybe something
along the lines:
rtx orig_reg = regno_reg_rtx[regno];
machine_mode m1 = GET_MODE (orig_reg);
machine_mode m2 = GE
On Aug 08 2024, Jeff Law via Gcc wrote:
> It just seems to work for me, but most of what I do is
> cross builds, but QEMU+binfmt to allow running the risc-v binaries
> seamlessly.
qemu enables V by default.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510
On Thu, Aug 08, 2024 at 07:57:43AM -0600, Jeff Law wrote:
>
>
> On 8/8/24 6:26 AM, Stefan Schulze Frielinghaus wrote:
> > On Thu, Aug 08, 2024 at 06:03:13AM -0600, Jeff Law wrote:
> > >
> > >
> > > On 8/8/24 5:15 AM, Stefan Schulze Frielinghaus via Gcc wrote:
> > >
> > > >
> > > > However `(r
On 8/8/24 9:13 AM, Mark Wielaard wrote:
But I don't fully understand how the gcc testsuite detects whether rvv
is implemented. e.g. rvv.exp seems to just check whether the target is
RISC-V and if so just executes all tests assuming it can just set
-march=rv64gcv* and/or -mrvv-* and run the t
Hi,
On Tue, Aug 06, 2024 at 02:11:45PM -0600, Jeff Law wrote:
> On 8/6/24 1:50 PM, Florian Weimer wrote:
> >* Jeff Law via Gcc:
> >
> >>On 8/5/24 4:23 PM, Mark Wielaard wrote:
> >>
> >>>It was suggested to just ignore the machine has rvv since it isn't
> >>>1.0
> >>>compliant. So it is now configu
On 8/8/24 6:26 AM, Stefan Schulze Frielinghaus wrote:
On Thu, Aug 08, 2024 at 06:03:13AM -0600, Jeff Law wrote:
On 8/8/24 5:15 AM, Stefan Schulze Frielinghaus via Gcc wrote:
However `(reg:DI 61 [ MEM[(const union T *)p_2(D)] ])` referencing the
same pseudo in a different mode is not subs
Hi Claudiu,
Thanks a lot for the clarifications! Unfortunately, though I have looked at
what you suggested, I still can't quite understand how to emit and work
with RTL that will ultimately lower into the assembly required for TLS on
Windows in legitimize_tls_address :( I shall not test your patie
On Thu, Aug 08, 2024 at 06:03:13AM -0600, Jeff Law wrote:
>
>
> On 8/8/24 5:15 AM, Stefan Schulze Frielinghaus via Gcc wrote:
>
> >
> > However `(reg:DI 61 [ MEM[(const union T *)p_2(D)] ])` referencing the
> > same pseudo in a different mode is not substituted in insn 6 which
> > leads in the
On 8/8/24 5:15 AM, Stefan Schulze Frielinghaus via Gcc wrote:
However `(reg:DI 61 [ MEM[(const union T *)p_2(D)] ])` referencing the
same pseudo in a different mode is not substituted in insn 6 which
leads in the following to an error. The insn is emitted in
s390_expand_insv() during
There
Am 08.08.24 um 10:08 schrieb Amit Hiremath:
I know, I am looking for a solution without using __asm macro
I explained that, too. Did you even read my answer?
Johann
On Thu, Aug 8, 2024 at 1:20 PM Georg-Johann Lay
You have already asked that question (and got an answer) in gcc-help@:
Hi all,
While trying to fix the failing test gcc.dg/torture/pr111821.c on s390 I'm
stumbling across another problem. After ira we have
(note 4 1 18 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 18 4 2 2 (set (reg:DI 66)
(reg:DI 2 %r2 [ p ])) "/gcc/testsuite/gcc.dg/torture/pr111821.c":5:1
1503 {
On Thu, Aug 08, 2024 at 09:31:37AM GMT, Martin Uecker wrote:
> Am Donnerstag, dem 08.08.2024 um 02:36 +0200 schrieb Alejandro Colomar:
> > Hi Martin,
> >
> > Can we promote -Wno-sizeof-array-argument to a hard error? I don't
> > think there's any legitimate use sizeof() on such a parameter.
>
>
I know, I am looking for a solution without using __asm macro
On Thu, Aug 8, 2024 at 1:20 PM Georg-Johann Lay wrote:
> You have already asked that question (and got an answer) in gcc-help@:
>
> https://gcc.gnu.org/pipermail/gcc-help/2024-August/thread.html#143628
>
> Johann
>
> Am 08.08.24 um 03
On Thu, Aug 8, 2024 at 3:56 AM Amit Hiremath wrote:
>
> Hello,
>
> I want to add custom single precision floating point sine, cosine, exp
> instructions to risc-v gnu tool chain, and I have designed hardware for
> this. I was going through tutorials on how to add custom instructions at:
> https://
You have already asked that question (and got an answer) in gcc-help@:
https://gcc.gnu.org/pipermail/gcc-help/2024-August/thread.html#143628
Johann
Am 08.08.24 um 03:54 schrieb Amit Hiremath:
Hello,
I want to add custom single precision floating point sine, cosine, exp
instructions to risc-v
Am Donnerstag, dem 08.08.2024 um 02:36 +0200 schrieb Alejandro Colomar:
> Hi Martin,
>
> Can we promote -Wno-sizeof-array-argument to a hard error? I don't
> think there's any legitimate use sizeof() on such a parameter.
I am a bit worried that it might prevent people from adding size informatio
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