Re: Indirect memory addresses vs. lra

On Sat, Aug 10, 2019 at 11:12:18AM -0500, Segher Boessenkool wrote: Hi! On Sat, Aug 10, 2019 at 08:05:53AM +0200, John Darrington wrote: > Choosing alt 5 in insn 14: (0) m (1) m {*movsi} >14: [r40:PSI+0x20]=[r41:PSI] > Inserting insn reload before: >

gcc-10-20190811 is now available

Snapshot gcc-10-20190811 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/10-20190811/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 10 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/trunk revision

Re: Expansion of narrowing math built-ins into power instructions

Hi Tejas, On Sat, Aug 10, 2019 at 04:00:53PM +0530, Tejas Joshi wrote: > +(define_expand "add_truncdfsf3" > + [(set (float_extend:DF (match_operand:SF 0 "gpc_reg_operand")) > + (plus:DF (match_operand:DF 1 "gpc_reg_operand") > + (match_operand:DF 2 "gpc_reg_operand")))] > + "TAR

SSA Trees and Lockless Implementation

Greetings, It seems possible after looking at the SSA dominator trees briefly to make them lockless at least partly for insertion/deletion/removal of both standard SSA nodes and PHI nodes. Am I right in assuming this or our there some subtle details that I'm missing when looking at and understandi

Re: Expansion of narrowing math built-ins into power instructions

Hello. > with it, but first get DP->SP (fadd) working? Can you please review what have I have been trying and facing the issues on patch : Thanks, Tejas On Sun, 11 Aug 2019 at 12:50, Segher Boessenkool wrote: > > Hi Tejas, > > On Sun, Aug 11,

Re: Expansion of narrowing math built-ins into power instructions

Hi Tejas, On Sun, Aug 11, 2019 at 10:34:26AM +0530, Tejas Joshi wrote: > > As far as I understand that flag should set the behaviour of the fadd > > function, not the __builtin_fadd one. So I don't know. > > According to ISO/IEC TS 18661, I am supposed to implement the fadd > variants for foldin