Re: For which gcc release is going to be foreseen the support for the Coroutines TS extension?

On 06/04/2018 07:36 PM, Jonathan Wakely wrote: On 4 June 2018 at 18:32, Marco Ippolito wrote: Hi all, clang and VS2017 already support the Coroutines TS extensions. For which gcc release is going to be foreseen the support for the Coroutines TS extension? This has been discussed recently, sea

Re: Project Ranger

On 06/04/2018 11:21 AM, Richard Biener wrote: On Mon, Jun 4, 2018 at 5:17 PM Richard Biener wrote:> On Fri, Jun 1, 2018 at 10:38 PM Andrew MacLeod wrote: On 06/01/2018 05:48 AM, Richard Biener wrote: On Wed, May 30, 2018 at 1:53 AM Andrew MacLeod wrote: bah, gmail now completely mangles qu

Re: Project Ranger

On 06/04/2018 11:17 AM, Richard Biener wrote: It wont be perfect however as many of those routines are written with the assumption that ranges are either a single range or an anti range. we no longer have that restriction and we will diverge in those cases. But having 1 single range or N ran

Re: Solaris issues

Hi Paul, >> In Solaris 11.4, there were some changes here for better GNU (bug) >> compatibility, so there's only a single .rodata section here. >> However, >> there's nothing wrong with how Solaris ld behaved before: I'd claim >> this >> is a scalability bug in valgrind: ELF objects can have very

Re: Solaris issues

- Original Message - > Hi Paul, [snip - lots of .rodata sections] > > those sections are in libstdc++.so. They can be found in the input > objects used to created libstdc++.so on Linux and Solaris alike, due > to > the use of -fdata-sections (via SECTION_FLAGS) in libstdc++. > > Howev

Salesforce Accounts

Hi, I am curious to know if you would be interested in acquiring Salesforce Users List. Information fields: Names, Title, Email, Phone, Company Name, Company URL, Company physical address, SIC Code, Industry, Company Size (Revenue and Employee). We also have related product users like:

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 06/05/18 13:30, Richard Biener wrote: > On Mon, Jun 4, 2018 at 8:11 PM Laszlo Ersek wrote: >> >> Hi! >> >> Apologies if this isn't the right place for asking. For the problem >> statement, I'll simply steal Ard's writeup [1]: >> >>> KVM on ARM refuses to decode load/store instructions used to p

Re: Solaris issues

Hi Paul, > I was only talking about adding support to aligned new/delete on Valgrind > (here is the bugzilla entry I created if you are interested > https://bugs.kde.org/show_bug.cgi?id=388787 > ) > > On Solaris (I’m using 11.3) Valgrind is having probl

Re: How to debug .md file?

On 06/05/2018 09:14 AM, DeepaBallari via gcc wrote: > Hello,I'm a newbie to GCC.Have done some changes to .md file(specifically > peephole.md) and the changes are not taking place.How to debug the .md file ? > Thanks! > Hi. .md files are transformed using gen* tools into C files. There's small

Re: aliasing between internal zero-length-arrays and other members

On Tue, Jun 05, 2018 at 01:38:21PM +0200, Richard Biener wrote: > On Tue, Jun 5, 2018 at 1:39 AM Martin Sebor wrote: > > > > GCC silently (without -Wpedantic) accepts declarations of zero > > length arrays that are followed by other members in the same > > struct, such as in: > > > >struct A {

Re: aliasing between internal zero-length-arrays and other members

On Tue, Jun 5, 2018 at 1:39 AM Martin Sebor wrote: > > GCC silently (without -Wpedantic) accepts declarations of zero > length arrays that are followed by other members in the same > struct, such as in: > >struct A { char a, b[0], c; }; > > Is it intended that accesses to elements of such arra

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On Mon, Jun 4, 2018 at 8:11 PM Laszlo Ersek wrote: > > Hi! > > Apologies if this isn't the right place for asking. For the problem > statement, I'll simply steal Ard's writeup [1]: > > > KVM on ARM refuses to decode load/store instructions used to perform > > I/O to emulated devices, and instead r

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On Tue, Jun 5, 2018 at 9:16 AM, Laszlo Ersek wrote: > On 06/05/18 08:04, Ard Biesheuvel wrote: >> On 4 June 2018 at 20:10, Laszlo Ersek wrote: >>> Hi! >>> >>> Apologies if this isn't the right place for asking. For the problem >>> statement, I'll simply steal Ard's writeup [1]: >>> KVM on AR

Re: __builtin_isnormal question

On 06/04/2018 09:44 PM, Steve Ellcey wrote: > 0.0 is a normal (as opposed to a denormalized) number isn't > it? Or is zero special? In addition to the other answers, yes, zero is special. Normal numbers in IEEE-754 have an implicit leading 1 bit. Zero is a case of a denormal number. -- Andrew

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 06/05/18 10:56, Ard Biesheuvel wrote: > On 5 June 2018 at 10:54, Laszlo Ersek wrote: >> On 06/05/18 10:23, Ard Biesheuvel wrote: >>> On 5 June 2018 at 10:18, Ard Biesheuvel wrote: On 5 June 2018 at 10:16, Laszlo Ersek wrote: >> > To my understanding, Daniel has the opposite preferenc

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 5 June 2018 at 10:54, Laszlo Ersek wrote: > On 06/05/18 10:23, Ard Biesheuvel wrote: >> On 5 June 2018 at 10:18, Ard Biesheuvel wrote: >>> On 5 June 2018 at 10:16, Laszlo Ersek wrote: > To my understanding, Daniel has the opposite preference; namely, the above approach doesn't scale

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 06/05/18 10:23, Ard Biesheuvel wrote: > On 5 June 2018 at 10:18, Ard Biesheuvel wrote: >> On 5 June 2018 at 10:16, Laszlo Ersek wrote: >>> To my understanding, Daniel has the opposite preference; namely, the >>> above approach doesn't scale to a large and moving target like the >>> kernel. Be

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 06/05/18 10:18, Ard Biesheuvel wrote: > On 5 June 2018 at 10:16, Laszlo Ersek wrote: >> On 06/05/18 08:04, Ard Biesheuvel wrote: >>> On 4 June 2018 at 20:10, Laszlo Ersek wrote: Hi! Apologies if this isn't the right place for asking. For the problem statement, I'll simply s

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

(I hit 'Send' too soon, apologies for the two stage reply) On 5 June 2018 at 10:18, Ard Biesheuvel wrote: > On 5 June 2018 at 10:16, Laszlo Ersek wrote: >> On 06/05/18 08:04, Ard Biesheuvel wrote: >>> On 4 June 2018 at 20:10, Laszlo Ersek wrote: Hi! Apologies if this isn't the ri

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 5 June 2018 at 10:16, Laszlo Ersek wrote: > On 06/05/18 08:04, Ard Biesheuvel wrote: >> On 4 June 2018 at 20:10, Laszlo Ersek wrote: >>> Hi! >>> >>> Apologies if this isn't the right place for asking. For the problem >>> statement, I'll simply steal Ard's writeup [1]: >>> KVM on ARM refus

Re: code-gen options for disabling multi-operand AArch64 and ARM instructions

On 06/05/18 08:04, Ard Biesheuvel wrote: > On 4 June 2018 at 20:10, Laszlo Ersek wrote: >> Hi! >> >> Apologies if this isn't the right place for asking. For the problem >> statement, I'll simply steal Ard's writeup [1]: >> >>> KVM on ARM refuses to decode load/store instructions used to perform >>

How to debug .md file?

Hello,I'm a newbie to GCC.Have done some changes to .md file(specifically peephole.md) and the changes are not taking place.How to debug the .md file ? Thanks!