Thank you, David, and the rest of the Steering Committee, for
welcoming us into the GCC community. I look forward to working
together.
On Wed, Jan 18, 2017 at 7:50 AM, David Edelsohn wrote:
> I am pleased to announce that the GCC Steering Committee has
> accepted the RISC-V port for incl
On 01/17/2017 09:00 AM, Torvald Riegel wrote:
I think the ABI should set a baseline for each architecture, and the
baseline decides whether something is inlinable or not. Thus, the
x86_64 ABI would make __int128 operations not imlinable (because of the
issues with cmpxchg16b, see above).
If use
On 01/18/2017 12:31 PM, Steve Silva wrote:
Hi All,
I just wanted to thank you for your help; I was able to fix the problem with
the following RTL
(define_expand "addhi3"
[(set (match_operand:HI 0 "nonimmediate_operand")
(plus:HI (match_operand:HI 1 "nonimmediate_operand")
(match_operand:HI 2
Hi All,
I just wanted to thank you for your help; I was able to fix the problem with
the following RTL
(define_expand "addhi3"
[(set (match_operand:HI 0 "nonimmediate_operand")
(plus:HI (match_operand:HI 1 "nonimmediate_operand")
(match_operand:HI 2 "general_operand")))]
""
{
if((GET_CODE
I am pleased to announce that the GCC Steering Committee has
accepted the RISC-V port for inclusion in GCC and appointed
Palmer Dabbelt and Andrew Waterman as co-maintainers.
The patches still require approval by a Global Reviewer, and the
timing to possibly land the patches in GCC
On 17.01.2017 21:41, Steve Silva via gcc wrote:
Hi Nathan,
Thanks for your advice. I retooled the addhi3 sequence to look like this:
(define_expand "addhi3"
[(set (match_operand:HI 0 "snap_mem_or_reg""+a,m")
(plus:HI (match_operand:HI 1 "snap_mem_or_reg" "%0,0")
(match_operand:HI 2 "genera
