I’m writing to alert the community to my intention to implement improvements to
the calculations of basic block frequencies during loop unrolling
optimizations. My work is sponsored by IBM and is motivated by an observation
that certain loop optimizations are being confused by the incorrect bl
On Fri, Sep 11, 2015 at 04:31:37PM +0100, Nikolai Bozhenov wrote:
> Hi!
>
> Recently I got somewhat confused by Cortex-A57 pipeline description in
> GCC and
> I would be grateful if you could help me understand a few unclear points.
Sure,
> Particularly I am interested in how memory operations
Hi!
Recently I got somewhat confused by Cortex-A57 pipeline description in
GCC and
I would be grateful if you could help me understand a few unclear points.
Particularly I am interested in how memory operations (loads/stores) are
scheduled. It seems that according to the cortex-a57.md file, fi
