On August 14, 2015 5:03:58 PM GMT+02:00, Ajit Kumar Agarwal
wrote:
>
>
>-Original Message-
>From: Richard Biener [mailto:richard.guent...@gmail.com]
>Sent: Monday, August 03, 2015 2:59 PM
>To: Ajit Kumar Agarwal
>Cc: Jeff Law; gcc@gcc.gnu.org; Vinod Kathail; Shail Aditya Gupta;
>Vidhumou
On 14/08/15 16:31, Jeff Law wrote:
On 08/14/2015 03:05 AM, Kyrill Tkachov wrote:
The problem I'm trying to solve can be expressed in this way: "An
insn that satisfies predicate pred_p (insn) cannot appear exactly N
insns apart from another insn 'insn2' that satisfies pred_p (insn2).
N is a cons
On 08/14/2015 03:05 AM, Kyrill Tkachov wrote:
The problem I'm trying to solve can be expressed in this way: "An
insn that satisfies predicate pred_p (insn) cannot appear exactly N
insns apart from another insn 'insn2' that satisfies pred_p (insn2).
N is a constant". So, the problem here is that
-Original Message-
From: Richard Biener [mailto:richard.guent...@gmail.com]
Sent: Monday, August 03, 2015 2:59 PM
To: Ajit Kumar Agarwal
Cc: Jeff Law; gcc@gcc.gnu.org; Vinod Kathail; Shail Aditya Gupta; Vidhumouli
Hunsigida; Nagaraju Mekala
Subject: Re: vectorization cost macro TARGET_V
[Alan wrote:]
> Interesting, thanks. For what kind of architecture are these -
You are welcome.
You raised 2 or 3 good points, I think.
First: the numbers are all from builds on and for the AMD64 ISA, AKA "x86_64".
My apologies for forgetting to mention that vital fact.
Second: I did not t
Abe wrote:
Dear all,
Overall, I think the WIP new if converter is holding up
relatively well, but there is obviously opportunity to do better,
at least if the numbers mean what they look like they mean,
i.e. the old converter`s code was fully OK and so is the new one`s.
By "fully OK" I mean e.g.
On Fri, Aug 14, 2015 at 8:20 AM, Andrey Semashev
wrote:
> On 14.08.2015 13:19, Jonathan Wakely wrote:
>>
>> On 14 August 2015 at 10:54, Andrey Semashev
>> wrote:
>>
>>> Otherwise I cannot see how (x==0 && y==0) could happen. The last load in
>>> each thread is sequenced after the first seq_cst st
On 14.08.2015 13:19, Jonathan Wakely wrote:
On 14 August 2015 at 10:54, Andrey Semashev wrote:
Otherwise I cannot see how (x==0 && y==0) could happen. The last load in
each thread is sequenced after the first seq_cst store and both stores are
ordered with respect to each other, so one of the t
On 14 August 2015 at 10:54, Andrey Semashev wrote:
> On 14.08.2015 11:51, Jonathan Wakely wrote:
>>
>> On 14 August 2015 at 01:37, Andrey Semashev wrote:
>>>
>>> 1. Is my test valid or is there a flaw that I'm missing?
>>
>>
>> The cppmem tool at http://svr-pes20-cppmem.cl.cam.ac.uk/cppmem/ shows
On 14.08.2015 11:51, Jonathan Wakely wrote:
On 14 August 2015 at 01:37, Andrey Semashev wrote:
1. Is my test valid or is there a flaw that I'm missing?
The cppmem tool at http://svr-pes20-cppmem.cl.cam.ac.uk/cppmem/ shows
that there are consistent executions where (x==0 && y==0) is true. I
use
I think I found explanation, the -fpeel-loops trigger some extra flags:
from "toplev.c":
/* web and rename-registers help when run after loop unrolling. */
if (flag_web == AUTODETECT_VALUE)
flag_web = flag_unroll_loops || flag_peel_loops;
if (flag_rename_registers == AUTODETECT_VALUE)
Hi Jeff,
On 13/08/15 17:20, Jeff Law wrote:
On 08/13/2015 05:06 AM, Kyrill Tkachov wrote:
Hi all,
I'm implementing a target-specific reorg pass, and one thing that I want
to do
is for a given insn in the stream to find an instruction
in the stream that I can swap it with, without violating any
On 14 August 2015 at 01:37, Andrey Semashev wrote:
> 1. Is my test valid or is there a flaw that I'm missing?
The cppmem tool at http://svr-pes20-cppmem.cl.cam.ac.uk/cppmem/ shows
that there are consistent executions where (x==0 && y==0) is true. I
used this code:
int main() {
atomic_int a = 0;
> Patch tested and committed with this ChangeLog entry.
>
> 2015-08-13 Ian Lance Taylor
>
> * dwarf.c (read_function_entry): Add vec_inlined parameter.
> Change all callers.
Thanks, this is great! I am going to submit the libgfortran patch to use
libbacktrace today.
Cheers,
FX
On Thu, Aug 13, 2015 at 6:26 PM, sa...@hederstierna.com
wrote:
> Hi
> I'm using an ARM thumb cross compiler for embedded systems and always do
> optimize for small size with -Os.
>
> Though I've experimented with optimization flags, and loop unrolling.
>
> Normally loop unrolling is always bad fo
On Fri, Aug 14, 2015 at 8:13 AM, Ajit Kumar Agarwal
wrote:
>
>
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Friday, August 14, 2015 11:30 AM
> To: Ajit Kumar Agarwal
> Cc: Jeff Law; gcc@gcc.gnu.org; Vinod Kathail; Shail Aditya Gupta; Vidhumouli
>
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